SLPS666 March   2018 CSD86336Q3D

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
    1.     Top View
      1.      Device Images
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Power Block Performance
    5. 5.5 Electrical Characteristics – Q1 Control FET
    6. 5.6 Electrical Characteristics – Q2 Sync FET
    7. 5.7 Typical Power Block Device Characteristics
    8. 5.8 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Equivalent System Performance
    2. 6.2 Power Loss Curves
    3. 6.3 Safe Operating Area (SOA) Curves
    4. 6.4 Normalized Curves
    5. 6.5 Calculating Power Loss and Safe Operating Area (SOA)
      1. 6.5.1 Design Example
      2. 6.5.2 Calculating Power Loss
      3. 6.5.3 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Recommended Schematic Overview
    2. 7.2 Recommended PCB Design Overview
      1. 7.2.1 Electrical Performance
      2. 7.2.2 Thermal Performance
  8. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Community Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Q3D Package Dimensions
    2. 9.2 Pin Configuration
    3. 9.3 Land Pattern Recommendation
    4. 9.4 Stencil Recommendation

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.