SLPS666
March 2018
CSD86336Q3D
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Top View
Device Images
4
Revision History
5
Specifications
5.1
Absolute Maximum Ratings
5.2
Recommended Operating Conditions
5.3
Thermal Information
5.4
Power Block Performance
5.5
Electrical Characteristics – Q1 Control FET
5.6
Electrical Characteristics – Q2 Sync FET
5.7
Typical Power Block Device Characteristics
5.8
Typical Power Block MOSFET Characteristics
6
Application and Implementation
6.1
Application Information
6.1.1
Equivalent System Performance
6.2
Power Loss Curves
6.3
Safe Operating Area (SOA) Curves
6.4
Normalized Curves
6.5
Calculating Power Loss and Safe Operating Area (SOA)
6.5.1
Design Example
6.5.2
Calculating Power Loss
6.5.3
Calculating SOA Adjustments
7
Layout
7.1
Recommended Schematic Overview
7.2
Recommended PCB Design Overview
7.2.1
Electrical Performance
7.2.2
Thermal Performance
8
Device and Documentation Support
8.1
Receiving Notification of Documentation Updates
8.2
Community Resources
8.3
Trademarks
8.4
Electrostatic Discharge Caution
8.5
Glossary
9
Mechanical, Packaging, and Orderable Information
9.1
Q3D Package Dimensions
9.2
Pin Configuration
9.3
Land Pattern Recommendation
9.4
Stencil Recommendation
Package Options
Mechanical Data (Package|Pins)
DPB|8
MPSS062C
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slps666_oa
slps666_pm
5.4
Power Block Performance
T
A
= 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
P
LOSS
Power loss
(1)
V
IN
= 12 V, V
GS
= 5 V, V
OUT
= 1.3 V, I
OUT
= 15 A,
ƒ
SW
= 500 kHz, L
OUT
= 950 nH, T
J
= 25°C
1.8
W
I
QVIN
V
IN
quiescent current
(1)
T
G
to T
GR
= 0 V, B
G
to P
GND
= 0 V, V
IN
= 12 V
10
µA
(1)
Measurement made with six 10-μF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V
IN
to P
GND
pins and
using a high-current 5-V driver IC.