SLPS666 March   2018 CSD86336Q3D

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
    1.     Top View
      1.      Device Images
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Power Block Performance
    5. 5.5 Electrical Characteristics – Q1 Control FET
    6. 5.6 Electrical Characteristics – Q2 Sync FET
    7. 5.7 Typical Power Block Device Characteristics
    8. 5.8 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Equivalent System Performance
    2. 6.2 Power Loss Curves
    3. 6.3 Safe Operating Area (SOA) Curves
    4. 6.4 Normalized Curves
    5. 6.5 Calculating Power Loss and Safe Operating Area (SOA)
      1. 6.5.1 Design Example
      2. 6.5.2 Calculating Power Loss
      3. 6.5.3 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Recommended Schematic Overview
    2. 7.2 Recommended PCB Design Overview
      1. 7.2.1 Electrical Performance
      2. 7.2.2 Thermal Performance
  8. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Community Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Q3D Package Dimensions
    2. 9.2 Pin Configuration
    3. 9.3 Land Pattern Recommendation
    4. 9.4 Stencil Recommendation

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.8 Typical Power Block MOSFET Characteristics

TA = 25°C, unless stated otherwise.
CSD86336Q3D D010_SLPS678.gif
Figure 8. Control MOSFET Saturation
CSD86336Q3D D012_SLPS678.gif
VDS = 5 V
Figure 10. Control MOSFET Transfer
CSD86336Q3D D014_SLPS678.gif
ID = 14 A VDD = 12.5 V
Figure 12. Control MOSFET Gate Charge
CSD86336Q3D D016_SLPS678.gif
Figure 14. Control MOSFET Capacitance
CSD86336Q3D D018_SLPS678.gif
ID = 250 µA
Figure 16. Control MOSFET VGS(th)
CSD86336Q3D D020_SLPS678.gif
Figure 18. Control MOSFET RDS(on) vs VGS
CSD86336Q3D D022_SLPS678.gif
ID = 14 A VGS = 4.5 V
Figure 20. Control MOSFET Normalized RDS(on)
CSD86336Q3D D024_SLPS678.gif
Figure 22. Control MOSFET Body Diode
CSD86336Q3D D026_SLPS678.gif
Figure 24. Control MOSFET Unclamped Inductive Switching
CSD86336Q3D D011_SLPS678.gif
Figure 9. Sync MOSFET Saturation
CSD86336Q3D D013_SLPS678.gif
VDS = 5 V
Figure 11. Sync MOSFET Transfer
CSD86336Q3D D015_SLPS678.gif
ID = 14 A VDD = 12.5 V
Figure 13. Sync MOSFET Gate Charge
CSD86336Q3D D017_SLPS678.gif
Figure 15. Sync MOSFET Capacitance
CSD86336Q3D D019_SLPS678.gif
ID = 250 µA
Figure 17. Sync MOSFET VGS(th)
CSD86336Q3D D021_SLPS678.gif
Figure 19. Sync MOSFET RDS(on) vs VGS
CSD86336Q3D D023_SLPS678.gif
ID = 14 A VGS = 4.5 V
Figure 21. Sync MOSFET Normalized RDS(on)
CSD86336Q3D D025_SLPS678.gif
Figure 23. Sync MOSFET Body Diode
CSD86336Q3D D027_SLPS678.gif
Figure 25. Sync MOSFET Unclamped Inductive Switching