6.1.1 Equivalent System Performance

Many of today's high-performance computing systems require low-power consumption in an effort to reduce system operating temperatures and improve overall system efficiency. This has created a major emphasis on improving the conversion efficiency of today’s synchronous buck topology. In particular, there has been an emphasis in improving the performance of the critical power semiconductor in the power stage of this application (see Figure 26). As such, optimization of the power semiconductors in these applications, needs to go beyond simply reducing R_DS(ON).

Figure 26. Synchronous Buck Topology

The CSD86356Q5D is part of TI’s power block product family which is a highly optimized product for use in a synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest generation silicon which has been optimized for switching performance, as well as minimizing losses associated with Q_GD, Q_GS, and Q_RR. Furthermore, TI’s patented packaging technology has minimized losses by nearly eliminating parasitic elements between the control FET and sync FET connections (see Figure 27). A key challenge solved by TI’s patented packaging technology is the system-level impact of Common Source Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increases switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI and modification of switching loss equations are outlined in TI’s Application Note Power Loss Calculation With Common Source Inductance Consideration for Synchronous Buck Converters (SLPA009).

Figure 27. Elimination of Common Source Inductance

The combination of TI’s latest generation silicon and optimized packaging technology has created a benchmarking solution that outperforms industry standard MOSFET chipsets of similar R_DS(ON) and MOSFET chipsets with lower R_DS(ON). Figure 28 and Figure 29 compare the efficiency and power loss performance of the CSD86356Q5D versus industry standard MOSFET chipsets commonly used in this type of application. This comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The performance of CSD86356Q5D clearly highlights the importance of considering the Effective AC On-Impedance (Z_DS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET R_DS(ON) specifications is not an indicator of the actual in-circuit performance when using TI’s Power Block technology.

VIN = 12 V	VOUT = 1.3 V	LOUT = 0.3 µH
ƒSW = 500 kHz	VDD= 5 V	TA = 25°C

Figure 28. Efficiency

VIN = 12 V	VOUT = 1.3 V	LOUT = 0.3 µH
ƒSW = 500 kHz	VDD = 5 V	TA = 25°C

Figure 29. Power Loss

Comparison of RDS(ON) vs ZDS(ON) compares the traditional DC measured R_DS(ON) of CSD86356Q5D versus its Z_DS(ON). This comparison takes into account the improved efficiency associated with TI’s patented packaging technology. As such, when comparing TI’s Power Block products to individually packaged discrete MOSFETs or dual MOSFETs in a standard package, the in-circuit switching performance of the solution must be considered. In this example, individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC measured R_DS(ON) values that are equivalent to CSD86356Q5D’s Z_DS(ON) value in order to have the same efficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged discrete MOSFETs or dual MOSFETs in a standard package.