SLPS665 March   2018 CSD86356Q5D

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
    1.     Top View
      1.      Device Images
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Power Block Performance
    5. 5.5 Electrical Characteristics – Q1 Control FET
    6. 5.6 Electrical Characteristics – Q2 Sync FET
    7. 5.7 Typical Power Block Device Characteristics
    8. 5.8 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Equivalent System Performance
        1. 6.1.1.1 Comparison of RDS(ON) vs ZDS(ON)
      2. 6.1.2 Power Loss Curves
      3. 6.1.3 Safe Operating Area (SOA) Curves
      4. 6.1.4 Normalized Curves
    2. 6.2 Typical Application
      1. 6.2.1 Design Example: Calculating Power Loss and SOA
      2. 6.2.2 Operating Conditions
        1. 6.2.2.1 Calculating Power Loss
        2. 6.2.2.2 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Recommended Schematic Overview
    2. 7.2 Recommended PCB Design Overview
      1. 7.2.1 Electrical Performance
      2. 7.2.2 Thermal Performance
  8. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Community Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Q5D Package Dimensions
    2. 9.2 Pin Configuration
    3. 9.3 Land Pattern Recommendation
    4. 9.4 Stencil Recommendation

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Typical Power Block Device Characteristics

TJ = 125°C, unless stated otherwise. The typical power block system characteristic curves and Figure 3 are based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper layers of 1-oz copper thickness. See Application and Implementation section for detailed explanation.
CSD86356Q5D D001_SLPS685.gif
VIN = 12 V VGS = 5 V VOUT = 1.3 V
ƒSW = 500 kHz LOUT = 0.3 µH
Figure 1. Power Loss vs Output Current
CSD86356Q5D D005_SLPS685.gif
VIN = 12 V VGS = 5 V VOUT = 1.3 V
ƒSW = 500 kHz LOUT = 0.3 µH
Figure 3. Typical Safe Operating Area (SOA)
CSD86356Q5D D002_SLPS685.gif
VIN = 12 V VGS = 5 V VOUT = 1.3 V
ƒSW = 500 kHz LOUT = 0.3 µH IOUT = 40 A
Figure 2. Normalized Power Loss vs Temperature
CSD86356Q5D D006_SLPS685.gif
VIN = 12 V VGS = 5 V VOUT = 1.3 V
LOUT = 0.3 µH IOUT = 40 A
Figure 4. Normalized Power Loss vs Switching Frequency
CSD86356Q5D D008_SLPS685.gif
VIN = 12 V VGS = 5 V ƒSW = 500 kHz
LOUT = 0.3 µH IOUT = 40 A
Figure 6. Normalized Power Loss vs Output Voltage
CSD86356Q5D D007_SLPS685.gif
VGS = 5 V VOUT = 1.3 V LOUT = 0.3 µH
ƒSW = 500 kHz IOUT = 40 A
Figure 5. Normalized Power Loss vs Input Voltage
CSD86356Q5D D009_SLPS685.gif
VIN = 12 V VGS = 5 V VOUT = 1.3 V
ƒSW = 500 kHz IOUT = 40 A
Figure 7. Normalized Power Loss vs Output Inductance