SLPS665 March   2018 CSD86356Q5D

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
    1.     Top View
      1.      Device Images
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Power Block Performance
    5. 5.5 Electrical Characteristics – Q1 Control FET
    6. 5.6 Electrical Characteristics – Q2 Sync FET
    7. 5.7 Typical Power Block Device Characteristics
    8. 5.8 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Equivalent System Performance
        1. 6.1.1.1 Comparison of RDS(ON) vs ZDS(ON)
      2. 6.1.2 Power Loss Curves
      3. 6.1.3 Safe Operating Area (SOA) Curves
      4. 6.1.4 Normalized Curves
    2. 6.2 Typical Application
      1. 6.2.1 Design Example: Calculating Power Loss and SOA
      2. 6.2.2 Operating Conditions
        1. 6.2.2.1 Calculating Power Loss
        2. 6.2.2.2 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Recommended Schematic Overview
    2. 7.2 Recommended PCB Design Overview
      1. 7.2.1 Electrical Performance
      2. 7.2.2 Thermal Performance
  8. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Community Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Q5D Package Dimensions
    2. 9.2 Pin Configuration
    3. 9.3 Land Pattern Recommendation
    4. 9.4 Stencil Recommendation

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.8 Typical Power Block MOSFET Characteristics

TA = 25°C, unless stated otherwise.
CSD86356Q5D D010_SLPS685.gif
Figure 8. Control MOSFET Saturation
CSD86356Q5D D012_SLPS685.gif
VDS = 5 V
Figure 10. Control MOSFET Transfer
CSD86356Q5D D014_SLPS685.gif
ID = 20 A VDS = 12.5 V
Figure 12. Control MOSFET Gate Charge
CSD86356Q5D D016_SLPS685.gif
ƒ = 1 MHz VGS = 0
Figure 14. Control MOSFET Capacitance
CSD86356Q5D D018_SLPS685.gif
ID = 250 µA
Figure 16. Control MOSFET VGS(th)
CSD86356Q5D D020_SLPS685.gif
Figure 18. Control MOSFET RDS(ON) vs VGS
CSD86356Q5D D022_SLPS685.gif
ID = 20 A
Figure 20. Control MOSFET Normalized RDS(ON)
CSD86356Q5D D024_SLPS685.gif
Figure 22. Control MOSFET Body Diode
CSD86356Q5D D026_SLPS685.gif
Figure 24. Control MOSFET Unclamped Inductive Switching
CSD86356Q5D D011_SLPS685.gif
Figure 9. Sync MOSFET Saturation
CSD86356Q5D D013_SLPS685.gif
VDS = 5 V
Figure 11. Sync MOSFET Transfer
CSD86356Q5D D015_SLPS685.gif
ID = 20 A VDS = 12.5 V
Figure 13. Sync MOSFET Gate Charge
CSD86356Q5D D017_SLPS685.gif
ƒ = 1 MHz VGS = 0
Figure 15. Sync MOSFET Capacitance
CSD86356Q5D D019_SLPS685.gif
ID = 250 µA
Figure 17. Sync MOSFET VGS(th)
CSD86356Q5D D021_SLPS685.gif
Figure 19. Sync MOSFET RDS(ON) vs VGS
CSD86356Q5D D023_SLPS685.gif
ID = 20 A
Figure 21. Sync MOSFET Normalized RDS(ON)
CSD86356Q5D D025_SLPS685.gif
Figure 23. Sync MOSFET Body Diode
CSD86356Q5D D027_SLPS685.gif
Figure 25. Sync MOSFET Unclamped Inductive Switching