SLPS327B September   2012  – April 2018 CSD86360Q5D

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
    1. 3.1 Top View
      1.      Device Images
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Power Block Performance
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Device Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Equivalent System Performance
      2. 6.1.2 Power Loss Curves
      3. 6.1.3 Safe Operating Area (SOA) Curves
      4. 6.1.4 Normalized Curves
    2. 6.2 Typical Application
      1. 6.2.1 Design Example: Calculating Power Loss and SOA
        1. 6.2.1.1 Operating Conditions
        2. 6.2.1.2 Calculating Power Loss
        3. 6.2.1.3 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Layout Guidelines
      1. 7.1.1 Electrical Performance
      2. 7.1.2 Thermal Performance
    2. 7.2 Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Community Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Q5D Package Dimensions
    2. 9.2 Land Pattern Recommendation
    3. 9.3 Stencil Recommendation
    4. 9.4 Q5D Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS Q1 Control FET Q2 Sync FET
MIN TYP MAX MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, IDS = 250 μA 25 25 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 20 V 1 1 μA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = +10 / –8 V 100 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, IDS = 250 μA 1 2.1 0.75 1.15 V
ZDS(on) Drain-to-source on-impedance VIN = 12 V, VDD = 5 V,
VOUT = 1.3 V IOUT = 25 A,
ƒSW = 500 kHz,
LOUT = 0.3 μH		 3.7 0.7 mΩ
gfs Transconductance VDS = 10 V, IDS = 20 A 113 169 S
DYNAMIC CHARACTERISTICS
CISS Input capacitance(1) VGS = 0 V, VDS = 12.5 V,
ƒ = 1 MHz		 1590 2060 3910 5080 pF
COSS Output capacitance(1) 840 1090 1970 2560 pF
CRSS Reverse transfer capacitance(1) 42 54 53 69 pF
RG Series gate resistance(1) 1.2 2.5 1.1 2.2 Ω
Qg Gate charge total (4.5 V)(1) VDS = 12.5 V,
IDS = 20 A		 9.7 12.6 23 30 nC
Qgd Gate charge gate-to-drain 2.3 3.6 nC
Qgs Gate charge gate-to-source 3.5 6.0 nC
Qg(th) Gate charge at Vth 1.9 3.5 nC
QOSS Output charge VDS = 12.5 V, VGS = 0 V 15.1 33 nC
td(on) Turnon delay time VDS = 12.5 V, VGS = 4.5 V,
IDS = 20 A, RG = 2 Ω		 8.4 9.5 ns
tr Rise time 20.4 14.8 ns
td(off) Turnoff delay time 14.5 29.3 ns
tf Fall time 4.3 6.6 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage IDS = 20 A, VGS = 0 V 0.85 1 0.75 0.82 V
Qrr Reverse recovery charge Vdd = 12 V, IF = 20 A,
di/dt = 300 A/μs		 27 50 nC
trr Reverse recovery time 22 34 ns
(1) Specified by design.

CSD86360Q5D M0189-01_LPS223.gif
Max RθJA = 50°C/W when mounted on 1 in2 (6.45 cm2) of 2-oz (0.071-mm) thick Cu.
CSD86360Q5D M0190-01_LPS223.gif
Max RθJA = 102°C/W when mounted on minimum pad area of 2-oz (0.071-mm) thick Cu.