SLPS350A February   2014  – January 2017 CSD87333Q3D

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Power Block Performance
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Device Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6 Applications
    1. 6.1 Power Loss Curves
    2. 6.2 Safe Operating Area (SOA) Curves
    3. 6.3 Normalized Curves
    4. 6.4 Calculating Power Loss and SOA
      1. 6.4.1 Design Example
      2. 6.4.2 Calculating Power Loss
      3. 6.4.3 Calculating SOA Adjustments
  7. 7 Recommended PCB Design Overview
    1. 7.1 Electrical Performance
  8. 8 Thermal Performance
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Community Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Q3D Package Dimensions
    2. 10.2 Pinout Configuration
    3. 10.3 Land Pattern Recommendation
    4. 10.4 Stencil Recommendation
    5. 10.5 Q3D Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Applications

The CSD87333Q3D NexFET power block is an optimized design for synchronous buck applications using 5-V gate drive. The control FET and sync FET silicon are parametrically tuned to yield the lowest power loss and highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems-centric environment. System-level performance curves such as power loss, SOA, and normalized graphs allow engineers to predict the product performance in the actual application.

6.1 Power Loss Curves

MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices. In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss performance curves. Figure 1 plots the power loss of the CSD87333Q3D as a function of load current. This curve is measured by configuring and running the CSD87333Q3D as it would be in the final application (see Figure 19). The measured power loss is the CSD87333Q3D loss and consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve.

Equation 1. Power loss = (VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT)

The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C under isothermal test conditions.

6.2 Safe Operating Area (SOA) Curves

The SOA curves in the CSD87333Q3D data sheet provides guidance on the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 5 outline the temperature and airflow conditions required for a given load current. The area under the curve dictates the safe operating area. All the curves are based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (T) and 6 copper layers of 1-oz copper thickness.

6.3 Normalized Curves

The normalized curves in the CSD87333Q3D data sheet provides guidance on the power loss and SOA adjustments based on their application specific needs. These curves show how the power loss and SOA boundaries adjust for a given set of system conditions. The primary Y-axis is the normalized change in power loss, and the secondary Y-axis is the change is system temperature required in order to comply with the SOA curve. The change in power loss is a multiplier for the power loss curve and the change in temperature is subtracted from the SOA curve.

CSD87333Q3D Typical_App.gif Figure 19. Typical Application

6.4 Calculating Power Loss and SOA

The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though the power loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following procedure outlines the steps the user should take to predict product performance for any set of system conditions.

6.4.1 Design Example

Operating conditions:

  • Output current = 10 A
  • Input voltage = 20 V
  • Output voltage = 1 V
  • Switching frequency = 1000 kHz
  • Inductor = 0.6 µH

6.4.2 Calculating Power Loss

  • Power loss at 10 A = 2.6 W (Figure 1)
  • Normalized power loss for input voltage ≈ 1.1 (Figure 7)
  • Normalized power loss for output voltage ≈ 0.96 (Figure 8)
  • Normalized power loss for switching frequency ≈ 1.04 (Figure 6)
  • Normalized power loss for output inductor ≈ 1.03 (Figure 9)
  • Final calculated power loss = 2.6 W × 1.1 × 0.96 × 1.04 × 1.03 ≈ 2.9 W

6.4.3 Calculating SOA Adjustments

  • SOA adjustment for input voltage ≈ 2°C (Figure 7)
  • SOA adjustment for output voltage ≈ - 0.2°C (Figure 8)
  • SOA adjustment for switching frequency ≈ 0.8°C (Figure 6)
  • SOA adjustment for output inductor ≈ 0.8°C (Figure 9)
  • Final calculated SOA adjustment = 2 + (-0.2) + 0.8 + 0.8 ≈ 3.4°C

In the Design Example, the estimated power loss of the CSD87333Q3D would increase to 2.9 W. In addition, the maximum allowable board or ambient temperature, or both, would have to decrease by 3.4°C. Figure 20 graphically shows how the SOA curve would be adjusted accordingly.

  1. Start by drawing a horizontal line from the application current to the SOA curve.
  2. Draw a vertical line from the SOA curve intercept down to the board or ambient temperature.
  3. Adjust the SOA board or ambient temperature by subtracting the temperature adjustment value.

In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient temperature of 3.4°C. In the event the adjustment value is a negative number, subtracting the negative number would yield an increase in allowable board or ambient temperature.

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CSD87333Q3D soa.png Figure 20. Power Block SOA