SLPS597D April   2017  – June 2024 CSD88599Q5DC

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Recommended Operating Conditions
    3. 4.3 Power Block Performance
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Typical Power Block Device Characteristics
    7. 4.7 Typical Power Block MOSFET Characteristics
  6. 5Application and Implementation
    1. 5.1 Application Information
    2. 5.2 Brushless DC Motor With Trapezoidal Control
    3. 5.3 Power Loss Curves
    4. 5.4 Safe Operating Area (SOA) Curve
    5. 5.5 Normalized Power Loss Curves
    6. 5.6 Design Example – Regulate Current to Maintain Safe Operation
    7. 5.7 Design Example – Regulate Board and Case Temperature to Maintain Safe Operation
    8. 5.8 Layout
      1. 5.8.1 Layout Guidelines
        1. 5.8.1.1 Electrical Performance
        2. 5.8.1.2 Thermal Considerations
      2. 5.8.2 Layout Example
  7. 6Device and Documentation Support
    1. 6.1 Receiving Notification of Documentation Updates
    2. 6.2 Support Resources
    3. 6.3 Trademarks
    4. 6.4 Electrostatic Discharge Caution
    5. 6.5 Glossary
  8. 7Revision History
  9. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

5.3 Power Loss Curves

CSD88599Q5DC was designed to operate up to 10-cell Li-Ion battery voltage applications ranging from 30V to 42V, typical 36V. For 11 and 12s, input voltages between 42V to 54V, RC snubbers are required for each switch-node U, V, and W. To reduce ringing, refer to the Section 5.8.1.1 section. In an effort to simplify the design process, Texas Instruments has provided measured power loss performance curves over a variety of typical conditions.

Figure 4-1 plots the CSD88599Q5DC power loss as a function of load current. The measured power loss includes both input conversion loss and gate drive loss.

Equation 1 is used to generate the power loss curve:

Equation 1. Power loss (W) = (VIN × IIN_SHUNT) + (VDD × IDD_SHUNT) – (VSW_AVG × IOUT)

The power loss measurements were made on the circuit shown in Figure 5-3. Power block devices for legs U and V, PB1 and PB2 were disabled by shorting the CSD88599Q5DC high-side and low-side FETs' gate-to-source terminals. Current shunt Iin_SHUNT provides input current and Idd_SHUNT provides driver supply current measurements. The winding current is measured from the DC load. An averaging circuit provides switch node W equivalent RMS voltage.

CSD88599Q5DC Power Loss Test CircuitFigure 5-3 Power Loss Test Circuit

The RMS current on the CSD88599Q5DC device depends on the motor winding current. For trapezoidal control, the MOSFET RMS current is calculated using Equation 2.


Equation 2. IRMS = IOUT × √2


Taking into consideration system tolerances with the current measurement scheme, the inverter design needs to withstand a 20% overload current.


Table 5-1 RMS and Overload Current Calculations
Winding RMS Current (A)CSD88599Q5DC IRMS (A)Overload 20% × IRMS (A)
202834
304251
405668