SLPS458A December   2013  – August 2014 CSD95373AQ5M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration And Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Power Stage Device Characteristics
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Feature Description
      1. 7.2.1 Powering CSD95373AQ5M And Gate Drivers
      2. 7.2.2 Undervoltage Lockout Protection (UVLO)
      3. 7.2.3 Enable
      4. 7.2.4 Power-Up Sequencing
      5. 7.2.5 PWM
      6. 7.2.6 FCCM
      7. 7.2.7 TAO/Fault (Thermal Analog Output/Protection Flag)
        1. 7.2.7.1 Overtemperature
        2. 7.2.7.2 Gate Drivers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Loss Curves
      2. 8.1.2 Safe Operating Curves (SOA)
      3. 8.1.3 Normalized Curves
      4. 8.1.4 Calculating Power Loss And SOA
        1. 8.1.4.1 Design Example
        2. 8.1.4.2 Calculating Power Loss
        3. 8.1.4.3 Calculating SOA Adjustments
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Recommended Schematic Overview
      2. 9.1.2 Recommended PCB Design Overview
      3. 9.1.3 Electrical Performance
      4. 9.1.4 Thermal Performance
      5. 9.1.5 Sensing Performance
  10. 10Application Schematic
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Drawing
    2. 12.2 Recommended PCB Land Pattern
    3. 12.3 Recommended Stencil Opening

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Layout

9.1 Layout Guidelines

9.1.1 Recommended Schematic Overview

There are several critical components that must be used in conjunction with this Power Stage device. Figure 17 shows a portion of a schematic with the critical components needed for proper operation.

  • C1: Bootstrap capacitor
  • R1: Bootstrap resistor
  • C4: Bypass capacitor for TAO
  • C3: Bypass capacitor for VDD
  • C5: Bypass capacitor for VIN to help with ringing reduction
  • C6: Bypass capacitor for VIN

Circuit_Schematic.pngFigure 17. Recommended Schematic

9.1.2 Recommended PCB Design Overview

There are two key system-level parameters that can be addressed with a proper PCB design: electrical and thermal performance. Properly optimizing the PCB layout yields maximum performance in both areas. A brief description on how to address each parameter follows.

9.1.3 Electrical Performance

The CSD95373AQ5M has the ability to switch at voltage rates greater than 10 kV/µs. Take special care with the PCB layout design and placement of the input capacitors, inductor, and output capacitors.

  • The placement of the input capacitors relative to VIN and PGND pins of CSD95373AQ5M device should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 18). The example in Figure 18 uses 1 × 3.3 nF 0402 50 V and 6 × 10 µF 1206 25 V ceramic capacitors (TDK Part # C3216X7R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the Power Stage C5, C8 and C6, C19 should follow in order.
  • The bootstrap capacitor CBOOT 0.1 µF 0603 16 V ceramic capacitor should be closely connected between BOOT and BOOT_R pins
  • The switching node of the output inductor should be placed relatively close to the Power Stage CSD95373AQ5M VSW pins. Minimizing the VSW node length between these two components reduces the PCB conduction losses and actually reduces the switching noise level. (1)
(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla

9.1.4 Thermal Performance

The CSD95373AQ5M has the ability to use the GND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that wicks down the via barrel:

  • Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
  • Use the smallest drill size allowed in your design. The example in Figure 18 uses vias with a 10 mil drill hole and a 26 mil capture pad.
  • Tent the opposite side of the via with solder-mask.

The number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities.

Recommended_Circuit_Layout_slps416.gifFigure 18. Recommended PCB Layout (Top-Down View)

9.1.5 Sensing Performance

The integrated temperature sensing technology built in the driver of the CSD95373AQ5M produces an analog signal that is proportional to the temperature of the lead-frame of the device, which is almost identical to the junction temperature of the Sync FET. To calculate the junction temperature based on the TAO voltage, use Equation 2. TAO should be bypassed to PGND with a 1 nF X7R ceramic capacitor for optimal performance. The TAO pin has limited sinking current capability to enable several power stages that are wire OR-ed together to report only the highest temperature (or fault condition if present). To ensure accurate temperature reporting, the TAO nets should be routed on a quiet inner layer between ground planes where possible. In addition, the TAO bypass capacitor should have a PGND pour on the layer directly beneath to ensure proper decoupling. The TAO net should always be shielded from VSW and VIN whenever possible.

Equation 2. TJ[C°] = (TAO[mV] - 400[mV]) / 8[mV/°C]