SLPS458A December   2013  – August 2014 CSD95373AQ5M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration And Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Power Stage Device Characteristics
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Feature Description
      1. 7.2.1 Powering CSD95373AQ5M And Gate Drivers
      2. 7.2.2 Undervoltage Lockout Protection (UVLO)
      3. 7.2.3 Enable
      4. 7.2.4 Power-Up Sequencing
      5. 7.2.5 PWM
      6. 7.2.6 FCCM
      7. 7.2.7 TAO/Fault (Thermal Analog Output/Protection Flag)
        1. 7.2.7.1 Overtemperature
        2. 7.2.7.2 Gate Drivers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Loss Curves
      2. 8.1.2 Safe Operating Curves (SOA)
      3. 8.1.3 Normalized Curves
      4. 8.1.4 Calculating Power Loss And SOA
        1. 8.1.4.1 Design Example
        2. 8.1.4.2 Calculating Power Loss
        3. 8.1.4.3 Calculating SOA Adjustments
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Recommended Schematic Overview
      2. 9.1.2 Recommended PCB Design Overview
      3. 9.1.3 Electrical Performance
      4. 9.1.4 Thermal Performance
      5. 9.1.5 Sensing Performance
  10. 10Application Schematic
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Drawing
    2. 12.2 Recommended PCB Land Pattern
    3. 12.3 Recommended Stencil Opening

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration And Functions

CSD95372A_pinout.pngFigure 1. Top View

PIN DESCRIPTION

PIN DESCRIPTION
NO. NAME
1, 2, 4 NC No Connect, must leave floating
3 ENABLE Enables device operation. If ENABLE = logic HIGH, turns on device. If ENABLE = logic LOW, the device is turned off and both MOSFET gates are actively pulled low. An internal 100 kΩ pulldown resistor pulls the ENABLE pin LOW if left floating.
5 VDD Supply Voltage to Gate Driver and internal circuitry
6 VSW Phase node connecting the HS MOSFET Source and LS MOSFET Drain - pin connection to the output inductor
7 VIN Input Voltage Pin. Connect input capacitors close to this pin.
8 BOOT_R Return path for HS gate driver, connected to VSW internally
9 BOOT Bootstrap capacitor connection. Connect a minimum of 0.1 µF 16 V X7R, ceramic capacitor from BOOT to BOOT_R pins. The bootstrap capacitor provides the charge to turn on the Control FET. The bootstrap diode is integrated.
10 FCCM This pin enables the Diode Emulation function. When this pin is held LOW, Diode Emulation Mode is enabled for Sync FET. When FCCM is HIGH, the device operated in Forced Continuous Conduction Mode. An internal 5 µA current source will pull the FCCM pin to VDD if left floating.
11 TAO/
FAULT		 Temperature amplifier output. Reports a voltage proportional to the die temperature. An ORing diode is integrated in the IC. When used in multiphase application, a single wire can be used to connect the TAO pins of all the ICs. Only the highest temperature is reported. TAO is pulled up to 3.3 V if Thermal Shutdown occurs. TAO should be bypassed to PGND with a 1 nF 16 V X7R ceramic capacitor.
12 PWM Pulse width modulated tri-state input from external controller. Logic LOW sets Control FET gate low and Sync FET gate high. Logic HIGH sets Control FET gate high and Sync FET gate low. Open or High Z sets both MOSFET gates low if greater than the tri-State Shutdown Hold-off Time (t3HT)
13 PGND Power Ground