SLPS430A August   2013  – August 2014 CSD95375Q4M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
  7. 7 Electrical Characteristics
  8. 8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1 Powering CSD95375Q4M And Gate Drivers
    3. 9.3 Undervoltage Lockout Protection (UVLO)
    4. 9.4 PWM Pin
    5. 9.5 SKIP# Pin
      1. 9.5.1 Zero Crossing (ZX) Operation
    6. 9.6 Integrated Boost-Switch
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Power Loss Curves
      2. 10.1.2 Safe Operating Curves (SOA)
      3. 10.1.3 Normalized Curves
      4. 10.1.4 Calculating Power Loss and SOA
        1. 10.1.4.1 Design Example
        2. 10.1.4.2 Calculating Power Loss
        3. 10.1.4.3 Calculating SOA Adjustments
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Recommended PCB Design Overview
      2. 11.1.2 Electrical Performance
      3. 11.1.3 Thermal Performance
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Drawing
    2. 13.2 Recommended PCB Land Pattern
    3. 13.3 Recommended Stencil Opening

Package Options

Mechanical Data (Package|Pins)
  • DPC|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings (1)

TA = 25°C (unless otherwise noted)
VALUE UNIT
MIN MAX
VIN to PGND –0.3 20 V
VSW to PGND , VIN to VSW –0.3 20 V
VSW to PGND, VIN to VSW (<10 ns) –7 23 V
VDD to PGND –0.3 6 V
PWM, SKIP# to PGND –0.3 6 V
BOOT to PGND –0.3 25 V
BOOT to PGND (<10 ns) –2 28 V
BOOT to BOOT_R –0.3 6 V
BOOT to BOOT_R (duty cycle <0.2%)
ESD Rating Human Body Model (HBM) 2000 V
Charged Device Model (CDM) 500 V
Power Dissipation, PD 8 W
Operating Temperature Range, TJ –40 150 °C
Storage Temperature Range, Tstg –55 150 °C
(1) Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability.

6.2 Recommended Operating Conditions

TA = 25° (unless otherwise noted)
MIN MAX UNIT
Gate Drive Voltage, VDD 4.5 5.5 V
Input Supply Voltage, VIN 16 V
Continuous Output Current, IOUT VIN = 12 V, VDD = 5 V, VOUT = 1.8 V,
ƒSW = 500 kHz, LOUT = 0.29 µH(1)		 25 A
Peak Output Current, IOUT-PK(2) 60 A
Switching Frequency, ƒSW CBST = 0.1 µF (min) 2000 kHz
On Time Duty Cycle 85%
Minimum PWM On Time 40 ns
Operating Temperature –40 125 °C
(1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(2) System conditions as defined in Note 1. Peak Output Current is applied for tp = 10 ms, duty cycle ≤1%

6.3 Thermal Information

TA = 25°C (unless otherwise noted)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-Case Thermal Resistance (Top of package)(1) 22.8 °C/W
RθJB Junction-to-Board Thermal Resistance(2) 2.5
(1) RθJC is determined with the device mounted on a 1-inch² (6.45 -cm²), 2-oz (.071-mm thick) Cu pad on a 1.5-inches × 1.5-inches,
0.06-inch (1.52-mm) thick FR4 board.
(2) RθJB value based on hottest board temperature within 1-mm of the package.