SLPS669A March   2017  – January 2018 CSD95490Q5MC

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
    1.     Typical Power Stage Efficiency and Power Loss
  4. 4Revision History
  5. 5Pin Configuration and Functions
    1.     Pin Functions
  6. 6Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
  7. 7Application Schematic
  8. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Community Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Mechanical Drawing
    2. 9.2 Recommended PCB Land Pattern
    3. 9.3 Recommended Stencil Opening

Package Options

Mechanical Data (Package|Pins)
  • DMC|12
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Top View
CSD95490Q5MC PinOut.gif

Pin Functions

PINDESCRIPTION
NAMENO.
REFIN 1 External reference voltage input for current sensing amplifier.
IOUT 2 Output of current sensing amplifier. V(IOUT) – V(REFIN) is proportional to the phase current.
LSET 3 A resistor from this pin to PGND pin sets the inductor value for the internal current sensing circuitry.
VDD 4 Supply voltage for gate drivers and internal circuitry.
VOS 5 Output voltage sensing pin for the internal current sensing circuitry.
SW 6 Phase node connecting the HS MOSFET source and LS MOSFET drain – pin connection to the output inductor.
VIN 7 Input voltage pin. Connect input capacitors close to this pin.
BOOTR 8 Return path for HS gate driver. It is connected to VSW internally.
BOOT 9 Bootstrap capacitor connection. Connect a minimum 0.1-µF, 16-V, X5R ceramic cap from BOOT to BOOTR pins. The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is integrated.
PWM 10 Tri-state input from external controller. Logic low sets control FET gate low and sync FET gate high. Logic high sets control FET gate high and sync FET gate low. Both MOSFET gates are set low if PWM stays in Hi-Z for greater than the tri-state shutdown hold-off time (t3HT).
EN/FCCM 11 This dual function pin either enables the diode emulation function or can be used as a simple enable for the device. When this pin is driven into the tri-state window and held there for more than the tri-state holdoff time, Diode Emulation Mode (DEM) is enabled for sync FET. When the pin is high, device operates in Forced Continuous Conduction Mode (FCCM). When the pin is low, both FETs are held off. An internal resistor pulls this pin low if left floating.
TAO/FAULT 12 Temperature Amplifier Output. Reports a voltage proportional to the IC temperature. An ORing diode is integrated in the IC. When used in multiphase application, a single wire can be used to connect the TAO pins of all the ICs. Only the highest temperature will be reported. TAO will be pulled up to 3.3 V if thermal shutdown, LSOC, or HSS detection circuit is tripped.
PGND 13 Power ground.