SLPS382D January   2013  – August 2016 CSD97374Q4M

 

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Powering CSD97374Q4M and Gate Drivers
    3. 7.3 Undervoltage Lockout Protection (UVLO)
    4. 7.4 PWM Pin
    5. 7.5 SKIP# Pin
      1. 7.5.1 Zero Crossing (ZX) Operation
    6. 7.6 Integrated Boost-Switch
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Power Loss Curves
    3. 8.3 Safe Operating Curves (SOA)
    4. 8.4 Normalized Curves
    5. 8.5 Calculating Power Loss and SOA
      1. 8.5.1 Design Example
      2. 8.5.2 Calculating Power Loss
      3. 8.5.3 Calculating SOA Adjustments
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Recommended PCB Design Overview
      2. 9.1.2 Electrical Performance
      3. 9.1.3 Thermal Performance
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Community Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Recommended PCB Land Pattern
    2. 11.2 Recommended Stencil Opening

Package Options

Mechanical Data (Package|Pins)
  • DPC|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The power stage CSD97374Q4M is a highly optimized design for synchronous buck applications using NexFET devices with a 5-V gate drive. The control FET and sync FET silicon are parametrically tuned to yield the lowest power loss and highest system efficiency. As a result, a rating method is used that is tailored towards a more systems-centric environment. The high-performance gate driver IC integrated in the package helps minimize the parasitics and results in extremely fast switching of the power MOSFETs. System-level performance curves such as power loss, safe operating area and normalized graphs allow engineers to predict the product performance in the actual application.

8.2 Power Loss Curves

MOSFET centric parameters such as RDS(ON) and Qgd are primarily needed by engineers to estimate the loss generated by the devices. In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss performance curves. Figure 1 plots the power loss of the CSD97374Q4M as a function of load current. This curve is measured by configuring and running the CSD97374Q4M as it would be in the final application (see Figure 14). The measured power loss is the CSD97374Q4M device power loss which consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve.

Equation 1. Power loss = (VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT)

The power loss curve in Figure 1 is measured at the maximum recommended junction temperature of
TJ = 125°C under isothermal test conditions.

8.3 Safe Operating Curves (SOA)

The SOA curves in the CSD97374Q4M data sheet give engineers guidance on the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss. Figure 3 and Figure 4 outline the temperature and airflow conditions required for a given load current. The area under the curve dictates the safe operating area. All the curves are based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (T) and 6 copper layers of 1-oz copper thickness.

8.4 Normalized Curves

The normalized curves in the CSD97374Q4M data sheet give engineers guidance on the power loss and SOA adjustments based on their application specific needs. These curves show how the power loss and SOA boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in power loss and the secondary Y-axis is the change is system temperature required in order to comply with the SOA curve. The change in power loss is a multiplier for the power loss curve and the change in temperature is subtracted from the SOA curve.

CSD97374Q4M CSD97374_Power_Loss_Test_Circuit.png Figure 14. Power Loss Test Circuit

8.5 Calculating Power Loss and SOA

The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though the power loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following procedure will outline the steps engineers should take to predict product performance for any set of system conditions.

8.5.1 Design Example

Operating conditions: output current (lOUT) = 15 A, input voltage (VIN ) = 7 V, output voltage (VOUT) = 1.5 V, switching frequency (ƒSW) = 800 kHz, output inductor (LOUT) = 0.2 µH

8.5.2 Calculating Power Loss

  • Typical power loss at 15 A = 2.8 W (Figure 1)
  • Normalized power loss for switching frequency ≈ 1.02 (Figure 5)
  • Normalized power loss for input voltage ≈ 1.07 (Figure 6)
  • Normalized power loss for output voltage ≈ 0.94 (Figure 7)
  • Normalized power loss for output inductor ≈ 1.08 (Figure 8)
  • Final calculated power loss = 2.8 W × 1.02 × 1.07 × 0.94 × 1.08 ≈ 3.1 W

8.5.3 Calculating SOA Adjustments

  • SOA adjustment for switching frequency ≈ 0.3°C (Figure 5)
  • SOA adjustment for input voltage ≈ 1.2°C (Figure 6)
  • SOA adjustment for output voltage ≈ –1.1°C (Figure 7)
  • SOA adjustment for output inductor ≈ 1.4°C (Figure 8)
  • Final calculated SOA adjustment = 0.3 + 1.2 + (–1.1) + 1.4 ≈ 1.8°C

CSD97374Q4M D017_SLPS382.gif Figure 15. Power Stage CSD97374Q4M SOA

In the design example above, the estimated power loss of the CSD97374Q4M would increase to 3.1 W. In addition, the maximum allowable board and/or ambient temperature would have to decrease by 1.8°C. Figure 15 graphically shows how the SOA curve would be adjusted accordingly.

  1. Start by drawing a horizontal line from the application current to the SOA curve.
  2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
  3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.

In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient temperature of 1.8°C. In the event the adjustment value is a negative number, subtracting the negative number would yield an increase in allowable board/ambient temperature.