SLPS382D January   2013  – August 2016 CSD97374Q4M

 

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Powering CSD97374Q4M and Gate Drivers
    3. 7.3 Undervoltage Lockout Protection (UVLO)
    4. 7.4 PWM Pin
    5. 7.5 SKIP# Pin
      1. 7.5.1 Zero Crossing (ZX) Operation
    6. 7.6 Integrated Boost-Switch
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Power Loss Curves
    3. 8.3 Safe Operating Curves (SOA)
    4. 8.4 Normalized Curves
    5. 8.5 Calculating Power Loss and SOA
      1. 8.5.1 Design Example
      2. 8.5.2 Calculating Power Loss
      3. 8.5.3 Calculating SOA Adjustments
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Recommended PCB Design Overview
      2. 9.1.2 Electrical Performance
      3. 9.1.3 Thermal Performance
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Community Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Recommended PCB Land Pattern
    2. 11.2 Recommended Stencil Opening

Package Options

Mechanical Data (Package|Pins)
  • DPC|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Functional Block Diagram

CSD97374Q4M Block_Diagram.gif Figure 11. Functional Block Diagram

7.2 Powering CSD97374Q4M and Gate Drivers

An external VDD voltage is required to supply the integrated gate driver IC and provide the necessary gate drive power for the MOSFETS. A 1-µF 10-V X5R or higher ceramic capacitor is recommended to bypass VDD pin to PGND. A bootstrap circuit to provide gate drive power for the control FET is also included. The bootstrap supply to drive the control FET is generated by connecting a 100-nF 16-V X5R ceramic capacitor between BOOT and BOOT_R pins. An optional RBOOT resistor can be used to slow down the turnon speed of the control FET and reduce voltage spikes on the VSW node. A typical 1-Ω to 4.7-Ω value is a compromise between switching loss and VSW spike amplitude.

7.3 Undervoltage Lockout Protection (UVLO)

The undervoltage lockout (UVLO) comparator evaluates the VDD voltage level. As VVDD rises, both the control FET and sync FET gates hold actively low at all times until VVDD reaches the higher UVLO threshold (VUVLO_H). Then the driver becomes operational and responds to PWM and SKIP# commands. If VDD falls below the lower UVLO threshold (VUVLO_L = VUVLO_H – hysteresis), the device disables the driver and drives the outputs of the control FET and sync FET gates actively low. Figure 12 shows this function.

CAUTION

Do not start the driver in the very low power mode (SKIP# = tri-state).

CSD97374Q4M v12218_lusba6.gif Figure 12. UVLO Operation

7.4 PWM Pin

The PWM pin incorporates an input tri-state function. The device forces the gate driver outputs to low when PWM is driven into the tri-state window and the driver enters a low-power state with zero exit latency. The pin incorporates a weak pullup to maintain the voltage within the tri-state window during low-power modes. Operation into and out of tri-state mode follows the timing diagram outlined in Figure 13.

When VDD reaches the UVLO_H level, a tri-state voltage range (window) is set for the PWM input voltage. The window is defined the PWM voltage range between PWM logic high (VIH) and logic low (VIL) thresholds. The device sets high-level input voltage and low-level input voltage threshold levels to accommodate both 3.3-V (typical) and 5-V (typical) PWM drive signals.

When the PWM exits tri-state, the driver enters CCM for a period of 4 µs, regardless of the state of the SKIP# pin. Normal operation requires this time period in order for the auto-zero comparator to resume.

CSD97374Q4M PWM_TriState_Timing_Diagram.gif Figure 13. PWM Tri-State Timing Diagram

7.5 SKIP# Pin

The SKIP# pin incorporates the input tri-state buffer as PWM. The function is somewhat different. When SKIP# is low, the zero crossing (ZX) detection comparator is enabled, and DCM mode operation occurs if the load current is less than the critical current. When SKIP# is high, the ZX comparator disables, and the converter enters FCCM mode. When both SKIP# and PWM are tri-stated, normal operation forces the gate driver outputs low and the driver enters a low-power state. In the low-power state, the UVLO comparator remains off to reduce quiescent current. When SKIP# is pulled low, the driver wakes up and is able to accept PWM pulses in less than 50 µs.

Table 1 shows the logic functions of UVLO, PWM, SKIP#, the control FET gate and the sync FET gate.

Table 1. Logic Functions of the Driver IC

UVLO PWM SKIP# SYNC FET GATE CONTROL FET GATE MODE
Active — — Low Low Disabled
Inactive Low Low High(1) Low DCM(1)
Inactive Low High High Low FCCM
Inactive High H or L Low High
Inactive Tri-state H or L Low Low LQ
Inactive — Tri-state Low Low ULQ
(1) Until zero crossing protection occurs.

7.5.1 Zero Crossing (ZX) Operation

The zero crossing comparator is adaptive for improved accuracy. As the output current decreases from a heavy load condition, the inductor current also reduces and eventually arrives at a valley, where it touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. The SW pin detects the zero-current condition. When this zero inductor current condition occurs, the ZX comparator turns off the rectifying MOSFET.

7.6 Integrated Boost-Switch

To maintain a BST-SW voltage close to VDD (to get lower conduction losses on the high-side FET), the conventional diode between the VDD pin and the BST pin is replaced by a FET which is gated by the DRVL signal.