The DAC084S085 is a full-featured, general-purpose QUAD 8-bit voltage-output digital-to-analog converter (DAC) that can operate from a single 2.7-V to 5.5-V supply and consumes 1.1 mW at 3 V and 2.5 mW at 5 V. The DAC084S085 is packaged in 10-pin SON and VSSOP packages. The 10-pin SON package makes the DAC084S085 the smallest QUAD DAC in its class. The on-chip output amplifier allows rail-to-rail output swing and the three wire serial interface operates at clock rates up to 40 MHz over the entire supply voltage range. Competitive devices are limited to 25-MHz clock rates at supply voltages in the 2.7-V to 3.6-V range. The serial interface is compatible with standard SPI, QSPI, MICROWIRE, and DSP interfaces.
The reference for the DAC084S085 serves all four channels and can vary in voltage between 1 V and VA, providing the widest possible output dynamic range. The DAC084S085 has a 16-bit input shift register that controls the outputs to be updated, the mode of operation, the power-down condition, and the binary input data. All four outputs can be updated simultaneously or individually depending on the setting of the two mode of operation bits.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DAC084S085 | VSSOP (10) | 3.00 mm × 3.00 mm |
WSON (10) | 3.00 mm × 3.00 mm |
Changes from E Revision (March 2013) to F Revision
Changes from D Revision (March 2013) to E Revision
A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device. A power-down feature reduces power consumption to less than a microWatt with three different termination options.
The low-power consumption and small packages of the DAC084S085 make it an excellent choice for use in battery-operated equipment.
The DAC084S085 is one of a family of pin-compatible DACs, including the 10-bit DAC104S085 and the 12-bit DAC124S085. The DAC084S085 operates over the extended industrial temperature range of −40°C to +105°C.
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | VA | Supply | Power supply input. Must be decoupled to GND. |
2 | VOUTA | Analog Output | Channel A Analog Output Voltage. |
3 | VOUTB | Analog Output | Channel B Analog Output Voltage. |
4 | VOUTC | Analog Output | Channel C Analog Output Voltage. |
5 | VOUTD | Analog Output | Channel D Analog Output Voltage. |
6 | GND | Ground | Ground reference for all on-chip circuitry. |
7 | VREFIN | Analog Input | Unbuffered reference voltage shared by all channels. Must be decoupled to GND. |
8 | DIN | Digital Input | Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC. |
9 | SYNC | Digital Input | Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. |
10 | SCLK | Digital Input | Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin. |
11 | PAD (WSON only) |
Ground | Exposed die attach pad can be connected to ground or left floating. Soldering the pad to the PCB offers optimal thermal performance and enhances package self-alignment during reflow. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage, VA | 6.5 | V | ||
Voltage on any input pin | −0.3 | 6.5 | V | |
Input current at any pin(4) | 10 | mA | ||
Package input current(4) | 20 | mA | ||
Power consumption at TA = 25°C | See(5) | |||
Junction temperature | 150 | °C | ||
Storage temperature, Tstg | −65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) | ±2500 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(3) | ±250 |
MIN | MAX | UNIT | |
---|---|---|---|
Operating temperature | −40 | 105 | °C |
Supply voltage, VA | 2.7 | 5.5 | V |
Reference voltage, VREFIN | 1 | VA | V |
Digital input voltage (2) | 0 | 5.5 | V |
Output load | 0 | 1500 | pF |
SCLK frequency | 40 | MHz |
THERMAL METRIC(1)(2) | DAC084S085 | UNIT | ||
---|---|---|---|---|
DGS (VSSOP) | DSC (WSON) | |||
10 PINS | 10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 240 | 250 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 53.3 | 40.7 | °C/W |
RθJB | Junction-to-board thermal resistance | 78.9 | 23.7 | °C/W |
ψJT | Junction-to-top characterization parameter | 4.8 | 0.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 77.6 | 23.8 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | 4.7 | °C/W |
PARAMETER | TEST CONDITIONS | MIN(1) | TYP(1) | MAX(1) | UNIT | |||
---|---|---|---|---|---|---|---|---|
STATIC PERFORMANCE | ||||||||
Resolution | TMIN ≤ TA ≤ TMAX | 8 | Bits | |||||
Monotonicity | TMIN ≤ TA ≤ TMAX | 8 | Bits | |||||
INL | Integral non-linearity | TA = 25°C | ±0.14 | LSB | ||||
TMIN ≤ TA ≤ TMAX | ±0.5 | |||||||
DNL | Differential non-linearity | VA = 2.7 V to 5.5 V | TA = 25°C | −0.02 | +0.04 | LSB | ||
TMIN ≤ TA ≤ TMAX | −0.13 | +0.18 | ||||||
ZE | Zero code error | IOUT = 0 mA | TA = 25°C | +4 | mV | |||
TMIN ≤ TA ≤ TMAX | +15 | |||||||
FSE | Full-scale error | IOUT = 0 mA | TA = 25°C | −0.1 | %FSR | |||
TMIN ≤ TA ≤ TMAX | −0.75 | |||||||
GE | Gain error | All ones Loaded to DAC register | TA = 25°C | −0.2 | %FSR | |||
TMIN ≤ TA ≤ TMAX | −1 | |||||||
ZCED | Zero code error drift | −20 | µV/°C | |||||
TC GE | Gain error tempco | VA = 3 V | −0.7 | ppm/°C | ||||
VA = 5 V | −1 | |||||||
OUTPUT CHARACTERISTICS | ||||||||
Output voltage range | See (2), TMIN ≤ TA ≤ TMAX | 0 | VREFIN | V | ||||
IOZ | High-impedance output leakage current(2) | TMIN ≤ TA ≤ TMAX | ±1 | µA | ||||
ZCO | Zero code output | VA = 3 V, IOUT = 200 µA | 1.3 | mV | ||||
VA = 3 V, IOUT = 1 mA | 6 | |||||||
VA = 5 V, IOUT = 200 µA | 7 | |||||||
VA = 5 V, IOUT = 1 mA | 10 | |||||||
FSO | Full scale output | VA = 3 V, IOUT = 200 µA | 2.984 | V | ||||
VA = 3 V, IOUT = 1 mA | 2.934 | |||||||
VA = 5 V, IOUT = 200 µA | 4.989 | |||||||
VA = 5 V, IOUT = 1 mA | 4.958 | |||||||
IOS | Output short-circuit current (source) | VA = 3 V, VOUT = 0 V, Input Code = FFh |
–56 | mA | ||||
VA = 5 V, VOUT = 0 V, Input Code = FFh |
–69 | |||||||
IOS | Output short-circuit current (sink) | VA = 3 V, VOUT = 3 V, Input Code = 00h |
52 | mA | ||||
VA = 5 V, VOUT = 5 V, Input Code = 00h |
75 | |||||||
IO | Continuous output current(2) |
Avaliable on each DAC output, TMIN ≤ TA ≤ TMAX | 11 | mA | ||||
CL | Maximum load capacitance | RL = ∞ | 1500 | pF | ||||
RL = 2 kΩ | 1500 | |||||||
ZOUT | DC output impedance | 7.5 | Ω | |||||
REFERENCE INPUT CHARACTERISTICS | ||||||||
VREFIN | Input range minimum | 0.2 | V | |||||
TMIN ≤ TA ≤ TMAX | 1 | |||||||
Input range maximum | TMIN ≤ TA ≤ TMAX | VA | V | |||||
Input impedance | 30 | kΩ | ||||||
LOGIC INPUT CHARACTERISTICS | ||||||||
IIN | Input current(2) | TMIN ≤ TA ≤ TMAX | ±1 | µA | ||||
VIL | Input low voltage(2) | VA = 3 V | TA = 25°C | 0.9 | V | |||
TMIN ≤ TA ≤ TMAX | 0.6 | |||||||
VA = 5 V | TA = 25°C | 1.5 | V | |||||
TMIN ≤ TA ≤ TMAX | 0.8 | |||||||
VIH | Input high voltage(2) | VA = 3 V | TA = 25°C | 1.4 | V | |||
TMIN ≤ TA ≤ TMAX | 2.1 | |||||||
VA = 5 V | TA = 25°C | 2.1 | V | |||||
TMIN ≤ TA ≤ TMAX | 2.4 | |||||||
CIN | Input capacitance(2) | TMIN ≤ TA ≤ TMAX | 3 | pF | ||||
POWER REQUIREMENTS | ||||||||
VA | Supply voltage minimum | TMIN ≤ TA ≤ TMAX | 2.7 | V | ||||
Supply voltage maximum | TMIN ≤ TA ≤ TMAX | 5.5 | V | |||||
IN | Normal supply current (output unloaded) | fSCLK = 30 MHz | VA = 2.7 V to 3.6 V |
TA = 25°C | 370 | µA | ||
TMIN ≤ TA ≤ TMAX | 485 | |||||||
VA = 4.5 V to 5.5 V |
TA = 25°C | 500 | µA | |||||
TMIN ≤ TA ≤ TMAX | 650 | |||||||
fSCLK = 0 MHz | VA = 2.7 V to 3.6 V |
350 | µA | |||||
VA = 4.5 V to 5.5 V |
460 | µA | ||||||
IPD | Power-down supply current (output unloaded, SYNC = DIN = 0 V after PD mode loaded) | All PD Modes(2) | VA = 2.7 V to 3.6 V |
TA = 25°C | 0.1 | µA | ||
TMIN ≤ TA ≤ TMAX | 1 | |||||||
VA = 4.5 V to 5.5 V |
TA = 25°C | 0.15 | µA | |||||
TMIN ≤ TA ≤ TMAX | 1 | |||||||
PN | Normal supply power (output unloaded) | fSCLK = 30 MHz | VA = 2.7 V to 3.6 V |
TA = 25°C | 1.1 | mW | ||
TMIN ≤ TA ≤ TMAX | 1.7 | |||||||
VA = 4.5 V to 5.5 V |
TA = 25°C | 2.5 | mW | |||||
TMIN ≤ TA ≤ TMAX | 3.6 | |||||||
fSCLK = 0 MHz | VA = 2.7 V to 3.6 V |
1.1 | mW | |||||
VA = 4.5 V to 5.5 V |
2.3 | mW | ||||||
PPD | Power-down supply power (output unloaded, SYNC = DIN = 0 V after PD mode loaded) | All PD Modes(2) | VA = 2.7 V to 3.6 V |
TA = 25°C | 0.3 | µW | ||
TMIN ≤ TA ≤ TMAX | 3.6 | |||||||
VA = 4.5 V to 5.5 V |
TA = 25°C | 0.8 | µW | |||||
TMIN ≤ TA ≤ TMAX | 5.5 |
MIN(1) | TYP(1) | MAX(1) | UNIT | ||||
---|---|---|---|---|---|---|---|
fSCLK | SCLK frequency | TA = 25°C | 40 | MHz | |||
TMIN ≤ TA ≤ TMAX | 30 | ||||||
ts | Output voltage settling time(2) | 40h to C0h code change RL = 2 kΩ, CL = 200 pF |
TA = 25°C | 3 | µs | ||
TMIN ≤ TA ≤ TMAX | 4.5 | ||||||
SR | Output slew rate | 1 | V/µs | ||||
Glitch impulse | Code change from 80h to 7Fh | 12 | nV-sec | ||||
Digital feedthrough | 0.5 | nV-sec | |||||
Digital crosstalk | 1 | nV-sec | |||||
DAC-to-DAC crosstalk | 3 | nV-sec | |||||
Multiplying bandwidth | VREFIN = 2.5 V ± 0.1 Vpp | 160 | kHz | ||||
Total harmonic distortion | VREFIN = 2.5 V ± 0.1 Vpp input frequency = 10 kHz |
70 | dB | ||||
tWU | Wake-up time | VA = 3 V | 6 | µsec | |||
VA = 5 V | 39 | µsec | |||||
1/fSCLK | SCLK cycle time | TA = 25°C | 25 | ns | |||
TMIN ≤ TA ≤ TMAX | 33 | ||||||
tCH | SCLK high time | TA = 25°C | 7 | ns | |||
TMIN ≤ TA ≤ TMAX | 10 | ||||||
tCL | SCLK low Time | TA = 25°C | 7 | ns | |||
TMIN ≤ TA ≤ TMAX | 10 | ||||||
tSS | SYNC set-up time prior to SCLK falling edge | TA = 25°C | 4 | ns | |||
TMIN ≤ TA ≤ TMAX | 10 | ||||||
tDS | Data set-up time prior to SCLK falling edge | TA = 25°C | 1.5 | ns | |||
TMIN ≤ TA ≤ TMAX | 3.5 | ||||||
tDH | Data hold time after SCLK falling edge | TA = 25°C | 1.5 | ns | |||
TMIN ≤ TA ≤ TMAX | 3.5 | ||||||
tCFSR | SCLK fall prior to rise of SYNC | TA = 25°C | 0 | ns | |||
TMIN ≤ TA ≤ TMAX | 3 | ||||||
tSYNC | SYNC high time | TA = 25°C | 6 | ns | |||
TMIN ≤ TA ≤ TMAX | 10 |
The DAC084S085 is a full-featured, general-purpose QUAD 8-bit voltage-output digital-to-analog converter (DAC) that can operate from a single 2.7-V to 5.5-V supply and consumes 1.1 mW at 3 V and 2.5 mW at 5 V. The on-chip output amplifier allows rail-to-rail output swing and the three wire serial interface operates at clock rates up to 40 MHz over the entire supply voltage range. The serial interface is compatible with standard SPI, QSPI, MICROWIRE, and DSP interfaces.
The reference for the DAC084S085 serves all four channels and can vary in voltage between 1 V and VA, providing the widest possible output dynamic range. The DAC084S085 has a 16-bit input shift register that controls the outputs to be updated, the mode of operation, the power-down condition, and the binary input data. All four outputs can be updated simultaneously or individually depending on the setting of the two mode of operation bits.
A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device. A power-down feature reduces power consumption to less than a microWatt with three different termination options.
The DAC084S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor strings that are followed by an output buffer. The reference voltage is externally applied at VREFIN and is shared by all four DACs.
For simplicity, a single resistor string is shown in Figure 29. This string consists of 256 equal valued resistors with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register determines which switch is closed, connecting the proper node to the amplifier. The input coding is straight binary with an ideal output voltage of:
where
The output amplifiers are rail-to-rail, providing an output voltage range of 0 V to VA when the reference is VA. All amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0 V and VA, in this case). For this reason, linearity is specified over less than the full output range of the DAC. However, if the reference is less than VA, there is only a loss in linearity in the lowest codes. The output capabilities of the amplifier are described in Electrical Characteristics.
The output amplifiers are capable of driving a load of 2 kΩ in parallel with 1500 pF to ground or to VA. The zero-code and full-scale outputs for given load currents are available in Electrical Characteristics.
The DAC084S085 uses a single external reference that is shared by all four channels. The reference pin, VREFIN, is not buffered and has an input impedance of 30 kΩ. TI recommends that VREFIN be driven by a voltage source with low output impedance. The reference voltage range is 1 V to VA, providing the widest possible output dynamic range.
The power-on reset circuit controls the output voltages of the four DACs during power-up. Upon application of power, the DAC registers are filled with zeros and the output voltages are 0 V. The outputs remain at 0 V until a valid write sequence is made to the DAC.
The DAC084S085 has four power-down modes, two of which are identical. In power-down mode, the supply current drops to 20 µA at 3 V and 30 µA at 5 V. The DAC084S085 is set in power-down mode by setting OP1 and OP0 to 11. Since this mode powers down all four DACs, the address bits, A1 and A0, are used to select different output terminations for the DAC outputs. Setting A1 and A0 to 00 or 11 causes the outputs to be tri-stated (a high impedance state). While setting A1 and A0 to 01 or 10 causes the outputs to be terminated by
2.5 kΩ or 100 kΩ to ground respectively (see Table 1).
A1 | A0 | OP1 | OP0 | OPERATING MODE |
---|---|---|---|---|
0 | 0 | 1 | 1 | High-Z outputs |
0 | 1 | 1 | 1 | 2.5 kΩ to GND |
1 | 0 | 1 | 1 | 100 kΩ to GND |
1 | 1 | 1 | 1 | High-Z outputs |
The bias generator, output amplifiers, resistor strings, and other linear circuitry are all shut down in any of the power-down modes. However, the contents of the DAC registers are unaffected when in power-down. Each DAC register maintains its value prior to the DAC084S085 being powered down unless it is changed during the write sequence which instructed it to recover from power down. Minimum power consumption is achieved in the power-down mode with SYNC and DIN idled low and SCLK disabled. The time to exit power-down (Wake-Up Time) is typically tWU µs as stated in Timing Requirements.
The three-wire interface is compatible with SPI™, QSPI, and MICROWIRE, as well as most DSPs and operates at clock rates up to 40 MHz. See Figure 1 for information on a write sequence.
A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked into the 16-bit serial input register on the falling edges of SCLK. To avoid misclocking data into the shift register, it is critical that SYNC not be brought low simultaneously with a falling edge of SCLK (see Figure 1). On the 16th falling clock edge, the last data bit is clocked in and the programmed function (a change in the DAC channel address, mode of operation, and/or register contents) is executed. At this point the SYNC line may be kept low or brought high. Any data and clock pulses after the 16th falling clock edge is ignored. In either case, SYNC must be brought high for the minimum specified time before the next write sequence is initiated with a falling edge of SYNC.
Because the SYNC and DIN buffers draw more current when they are high, they must be idled low between write sequences to minimize power consumption.
The input shift register, Figure 30, has 16 bits. The first two bits are address bits. They determine whether the register data is for DAC A, DAC B, DAC C, or DAC D. The address bits are followed by two bits that determine the mode of operation (writing to a DAC register without updating the outputs of all four DACs, writing to a DAC register and updating the outputs of all four DACs, writing to the register of all four DACs and updating their outputs, or powering down all four outputs). The final twelve bits of the shift register are the data bits. The data format is straight binary (MSB first, LSB last), with all 0s corresponding to an output of 0 V and all 1s corresponding to a full-scale output of VREFIN – 1 LSB. The contents of the serial input register are transferred to the DAC register on the sixteenth falling edge of SCLK. See Figure 1.
Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the data transfer to the shift register is aborted and the write sequence is invalid. Under this condition, the DAC register is not updated and there is no change in the mode of operation or in the DAC output voltages.
Interfacing the DAC084S085 to microprocessors and DSPs is quite simple.
Figure 31 shows a serial interface between the DAC084S085 and the ADSP-2101 or ADSP2103. The DSP must be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control register and must be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length. Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.
Figure 32 shows a serial interface between the DAC084S085 and the 80C51 or 80L51 microcontroller. The SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line P3.3. This line is taken low when data is transmitted to the DAC084S085. Because the 80C51 and 80L51 transmits 8-bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the P3.3 line must be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the second byte of data, after which port line P3.3 is brought high. The 80C51 and 80L51 transmit routine must recognize that the 80C51 and 80L51 transmits data with the LSB first while the DAC084S085 requires data with the MSB first.
Figure 33 shows a serial interface between the DAC084S085 and the 68HC11 microcontroller. The SYNC line of the DAC084S085 is driven from a port line (PC7 in the figure), similar to the 80C51 and 80L51.
The 68HC11 must be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the second byte of data to the DAC, after which PC7 must be raised to end the write sequence.
Figure 34 shows an interface between a Microwire compatible device and the DAC084S085. Data is clocked out on the rising edges of the SK signal. As a result, the SK of the Microwire device must be inverted before driving the SCLK of the DAC084S085.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The DAC084S085 is designed for single-supply operation and thus has a unipolar output. However, a bipolar output may be obtained with the circuit in Figure 35. This circuit provides an output voltage range of ±5 V. A rail-to-rail amplifier must be used if the amplifier supplies are limited to ±5 V.
The output voltage of this circuit for any code is found to be:
where
With VA = 5 V and R1 = R2,
A list of rail-to-rail amplifiers suitable for this application are indicated in Table 2.
AMP | PKGS | Typ VOS | Typ ISUPPLY |
---|---|---|---|
LMC7111 | DIP-8 SOT23-5 |
0.9 mV | 25 µA |
LM7301 | SO-8 SOT23-5 |
0.03 mV | 620 µA |
LM8261 | SOT23-5 | 0.7 mV | 1 mA |
Figure 36 shows Channel A of the DAC084S085 providing the drive or supply voltage for a bridge sensor. By having the sensor supply voltage adjustable, the output of the sensor can be optimized to the input level of the ADC monitoring it.
The output of the sensor is amplified by a fixed gain amplifier stage with a differential gain of 1 + 2 × (RF / RI). The advantage of this amplifier configuration is the high input impedance seen by the output of the bridge sensor. The disadvantage is the poor common-mode rejection ratio (CMRR). The common-mode voltage (VCM) of the bridge sensor is half of DAC output of Channel A. The VCM is amplified by a gain of 1 V/V by the amplifier stage and thus becomes the bias voltage for the input of the ADC121S705. Channel B of the DAC084S085 is providing the reference voltage to the ADC121S705. The reference for the ADC121S705 may be set to any voltage from 1 V to 5 V, providing the widest dynamic range possible.
The reference voltage for Channel A and B is powered by an external 5-V power supply. Because the 5-V supply is common to the sensor supply voltage and the reference voltage of the ADC, fluctuations in the value of the
5-V supply has a minimal effect on the digital output code of the ADC. This type of configuration is often referred to as a ratiometric design. For example, an increase of 5% to the 5-V supply causes the sensor supply voltage to increase by 5%. This causes the gain or sensitivity of the sensor to increase by 5%. The gain of the amplifier stage is unaffected by the change in supply voltage. The ADC121S705 on the other hand, also experiences a 5% increase to its reference voltage. This causes the size of the ADC's least significant bit (LSB) to increase by 5%. As a result of the gain of the sensor increasing by 5% and the LSB size of the ADC increasing by the same 5%, there is no net effect on the circuit's performance. It is assumed that the amplifier gain is set low enough to allow for a 5% increase in the sensor output. Otherwise, the increase in the sensor output level may cause the output of the amplifiers to clip.
While the simplicity of the DAC084S085 implies ease of use, it is important to recognize that the path from the reference input (VREFIN) to the VOUTs has essentially zero power supply rejection ratio (PSRR). Therefore, it is necessary to provide a noise-free supply voltage to VREFIN. To use the full dynamic range of the DAC084S085, the supply pin (VA) and VREFIN can be connected together and share the same supply voltage. Because the DAC084S085 consumes very little power, a reference source may be used as the reference input and/or the supply voltage. The advantages of using a reference source over a voltage regulator are accuracy and stability. Some low noise regulators can also be used. Listed below are a few reference and power supply options for the DAC084S085.
The LM4130, with its 0.05% accuracy over temperature, is a good choice as a reference source for the DAC084S085. The 4.096-V version is useful if a 0-V to 4.095-V output range is desirable or acceptable. Bypassing the LM4130 VIN pin with a 0.1-µF capacitor and the VOUT pin with a 2.2-µF capacitor improves stability and reduces output noise. The LM4130 comes in a space-saving 5-pin SOT-23.
Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a reference for the DAC084S085. It is available in 4.096-V and 5-V versions, and comes in a space-saving 3-pin SOT-23.
The minimum resistor value in the circuit of Figure 39 must be chosen such that the maximum current through the LM4050 does not exceed its 15-mA rating. The conditions for maximum current include the input voltage at its maximum, the LM4050 voltage at its minimum, and the DAC084S085 drawing zero current. The maximum resistor value must allow the LM4050 to draw more than its minimum current for regulation plus the maximum DAC084S085 current in full operation. The conditions for minimum current include the input voltage at its minimum, the LM4050 voltage at its maximum, the resistor value at its maximum due to tolerance, and the DAC084S085 draws its maximum current. These conditions can be summarized as:
and
where
The LP3985 is a low-noise, ultra-low dropout voltage regulator with a 3% accuracy over temperature. It is a good choice for applications that do not require a precision reference for the DAC084S085. It comes in 3-V, 3.3-V, and 5-V versions, among others, and sports a low 30-µV noise specification at low frequencies. Because low frequency noise is relatively difficult to filter, this specification could be important for some applications. The LP3985 comes in a space-saving 5-pin SOT-23 and 5-bump DSBGA packages.
An input capacitance of 1 µF without any ESR requirement is required at the LP3985 input, while a 1-µF ceramic capacitor with an ESR requirement of 5 mΩ to 500 mΩ is required at the output. Careful interpretation and understanding of the capacitor specification is required to ensure correct device operation.
The LP2980 is an ultra-low dropout regulator with a 0.5% or 1% accuracy over temperature, depending upon grade. It is available in 3-V, 3.3-V, and 5-V versions, among others.
Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor must be at least 1 µF over temperature, but values of 2.2 µF or more provides even better performance. The ESR of this capacitor must be within the range specified in the LP2980 data sheet. Surface-mount solid tantalum capacitors offer a good combination of small size and ESR. Ceramic capacitors are attractive due to their small size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic capacitors are typically not a good choice due to their large size and have ESR values that may be too high at low temperatures.
For best accuracy and minimum noise, the printed-circuit board containing the DAC084S085 must have separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes. Both of these planes must be located in the same board layer. There must be a single ground plane. A single ground plane is preferred if digital return current does not flow through the analog ground area. Frequently a single ground plane design uses a fencing technique to prevent the mixing of analog and digital ground current. Separate ground planes must only be used when the fencing technique is inadequate. The separate ground planes must be connected in one place, preferably near the DAC084S085. Special care is required to ensure that digital signals with fast edge rates do not pass over split ground planes. They must always have a continuous return path below their traces.
The DAC084S085 power supply must be bypassed with a 10-µF and a 0.1-µF capacitor as close as possible to the device with the 0.1 µF right at the device supply pin. The 10-µF capacitor must be a tantalum type and the 0.1-µF capacitor must be a low ESL, low ESR type. The power supply for the DAC084S085 must only be used for analog circuits.
Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the board. The clock and data lines must have controlled impedances.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of
1 LSB, which is VREF / 256 = VA / 256.
DAC-to-DAC CROSSTALK is the glitch impulse transferred to a DAC output in response to a full-scale change in the output of another DAC.
DIGITAL CROSSTALK is the glitch impulse transferred to a DAC output at mid-scale in response to a full-scale change in the input register of another DAC.
DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data bus.
FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFh) loaded into the DAC and the value of VA x 255 / 256.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and Full-Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error.
GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register changes. It is specified as the area of the glitch in nanovolt-seconds.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line through the input to output transfer function. The deviation of any given code from this straight line is measured from the center of that code value. The end point method is used. INL for this product is specified over a limited range, per Electrical Characteristics.
LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is
where
MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output stability maintained.
MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when the input code increases.
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is 1/2 of VA.
MULTIPLYING BANDWIDTH is the frequency at which the output amplitude falls 3dB below the input sine wave on VREFIN with a full-scale code loaded into the DAC.
POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from the power supply. The difference between the supply and output currents is the power consumed by the device without a load.
SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is updated.
TOTAL HARMONIC DISTORTION (THD) is the measure of the harmonics present at the output of the DACs with an ideal sine wave applied to VREFIN. THD is measured in dB.
WAKE-UP TIME is the time for the output to exit power-down mode. This is the time from the falling edge of the 16th SCLK pulse to when the output voltage deviates from the power-down voltage of 0 V.
ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 00h has been entered.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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