SNAS321G June 2005 – April 2016 DAC101S101 , DAC101S101-Q1
PRODUCTION DATA.
The DAC101S101 is a full-featured, general purpose 10-bit voltage-output digital-to-analog converter (DAC) that can operate from a single +2.7 V to 5.5 V supply and consumes just 175 µA of current at 3.6 Volts. The on-chip output amplifier allows rail-to-rail output swing and the three wire serial interface operates at clock rates up to 30 MHz over the specified supply voltage range and is compatible with standard SPI, QSPI, MICROWIRE and DSP interfaces. Competitive devices are limited to 20 MHz clock rates at supply voltages in the 2.7 V to 3.6 V range.
The supply voltage for the DAC101S101 serves as its voltage reference, providing the widest possible output dynamic range. A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device. A power-down feature reduces power consumption to less than a microWatt.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DAC101S101 | VSSOP (8) | 3.00 mm × 3.00 mm |
DAC101S101, DAC101S101-Q1 |
SOT-23 (6) | 1.60 mm × 2.90 mm |
Changes from F Revision (March 2013) to G Revision
Changes from E Revision (March 2013) to F Revision
The low power consumption and small packages of the DAC101S101 make it an excellent choice for use in battery operated equipment.
The DAC101S101 is a direct replacement for the AD5310 and is one of a family of pin compatible DACs, including the 8-bit DAC081S101 and the 12-bit DAC121S101. The DAC101S101 operates over the extended industrial temperature range of −40°C to +105°C while the DAC101S101Q operates over the Grade 1 automotive temperature range of −40°C to +125°C. The DAC101S101 is available in a 6-lead SOT and an 8-lead VSSOP and the DAC101S101Q is availabe in the 6-lead SOT only.
PIN | I/O(1) | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | DAC101S101 | DAC101S101-Q1 | |||
SOT-23 | VSSOP | SOT-23 | |||
DIN | 4 | 7 | 4 | I | Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC. |
GND | 2 | 8 | 2 | G | Ground reference for all on-chip circuitry. |
NC | – | 2,3 | – | – | No Connect. There is no internal connection to these pins. |
SCLK | 5 | 6 | 5 | I | Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin. |
SYNC | 6 | 5 | 6 | I | Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. |
VA | 3 | 1 | 3 | S | Power supply and Reference input. Should be decoupled to GND. |
VOUT | 1 | 4 | 1 | O | DAC Analog Output Voltage. |