DAC101S101 and DAC101S101Q-1 10-Bit Micro Power, RRO Digital-to-Analog Converter

1 Features

• DAC101S101Q is AEC-Q100 Grade 1 Qualified and is Manufactured on an Automotive Grade Flow.
• Ensured Monotonicity
• Low Power Operation
• Rail-to-Rail Voltage Output
• Power-on Reset to Zero Volts Output
• Wide Temperature Range of −40°C to +125°C
• Wide Power Supply Range of 2.7 V to 5.5 V
• Small Packages
• Power Down Feature
• Resolution 10 bits
• DNL +0.15, –0.05 LSB (typical)
• Output Settling Time 8 μs (typical)
• Zero Code Error 3.3 mV (typical)
• Full-Scale Error −0.06 %FS (typical)
• Power Consumption
  • Normal Mode, 0.63 mW (3.6 V) / 1.41 mW (5.5 V) typical
  • Power Down Mode, 0.14 μW (3.6 V) / 0.33 μW (5.5 V) typical

2 Applications

• Battery-Powered Instruments
• Digital Gain and Offset Adjustment
• Programmable Voltage & Current Sources
• Programmable Attenuators
• Automotive

3 Description

The DAC101S101 is a full-featured, general purpose 10-bit voltage-output digital-to-analog converter (DAC) that can operate from a single +2.7 V to 5.5 V supply and consumes just 175 µA of current at 3.6 Volts. The on-chip output amplifier allows rail-to-rail output swing and the three wire serial interface operates at clock rates up to 30 MHz over the specified supply voltage range and is compatible with standard SPI, QSPI, MICROWIRE and DSP interfaces. Competitive devices are limited to 20 MHz clock rates at supply voltages in the 2.7 V to 3.6 V range.

The supply voltage for the DAC101S101 serves as its voltage reference, providing the widest possible output dynamic range. A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device. A power-down feature reduces power consumption to less than a microWatt.

1. For all available packages, see the orderable addendum at the end of the data sheet.

DNL at V_A = 3 V

4 Revision History

Changes from F Revision (March 2013) to G Revision

• Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
• Updated Operating Conditions table to a Recommended Operating Conditions tableGo
• Updated Layout, Grounding, and Bypassing section to a Layout Guidelines sectionGo

Changes from E Revision (March 2013) to F Revision

• Changed layout of National Data Sheet to TI formatGo

5 Description (continued)

The low power consumption and small packages of the DAC101S101 make it an excellent choice for use in battery operated equipment.

The DAC101S101 is a direct replacement for the AD5310 and is one of a family of pin compatible DACs, including the 8-bit DAC081S101 and the 12-bit DAC121S101. The DAC101S101 operates over the extended industrial temperature range of −40°C to +105°C while the DAC101S101Q operates over the Grade 1 automotive temperature range of −40°C to +125°C. The DAC101S101 is available in a 6-lead SOT and an 8-lead VSSOP and the DAC101S101Q is availabe in the 6-lead SOT only.

6 Pin Configuration and Functions

7 Specifications

7.7 A.C. and Timing Requirements

The following specifications apply for V_A = +2.7 V to +5.5 V, R_L = 2 kΩ to GND, C_L = 200 pF to GND, f_SCLK = 30 MHz, input code range 12 to 1011, T_A = 25°C, unless otherwise specified.

							MIN(8)	TYP(8)	MAX(8)	UNIT
fSCLK	SCLK Frequency	DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C							30	MHz
ts	Output voltage settling time (9)	100h to 300h code change, RL = 2 kΩ		CL ≤ 200 pF				5		µs
					DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C				7.5
SR	Output slew rate							1		V/µs
	Glitch impulse	Code change from 200h to 1FFh						12		nV-sec
	Digital feedthrough							0.5		nV-sec
tWU	Wake-up time	VA = 5 V						6		µs
		VA = 3 V						39		µs
1/fSCLK	SCLK Cycle time	DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C					33			ns
tH	SCLK High time							5		ns
		DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C					13
tL	SCLK Low time							5		ns
		DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C					13
tSUCL	Set-up time SYNC to SCLK rising edge							−15		ns
		DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C					0
tSUD	Data set-up time							2.5		ns
		DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C					5
tDHD	Data hold time							2.5		ns
		DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C					4.5
tCS	SCLK fall to rise of SYNC	VA = 5 V						0		ns
					DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C		3
		VA = 3 V						−2		ns
					DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C		1
tSYNC	SYNC High time	2.7 ≤ VA ≤ 3.6						9		ns
					DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C		20
		3.6 ≤ VA ≤ 5.5						5		ns
					DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C		10

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.

(3) All voltages are measured with respect to GND = 0V, unless otherwise specified

(4) When the input voltage at any pin exceeds the power supplies (that is, less than GND, or greater than V_A), the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.

(5) The absolute maximum junction temperature (T_Jmax) for this device is 150°C. The maximum allowable power dissipation is dictated by T_Jmax, the junction-to-ambient thermal resistance (θ_JA), and the ambient temperature (T_A), and can be calculated using the formula P_DMAX = (T_Jmax − T_A) / θ_JA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

(6) The analog inputs are protected as shown below. Input voltage magnitudes up to V_A + 300 mV or to 300 mV below GND will not damage this device. However, errors in the conversion result can occur if any input goes above V_A or below GND by more than 100 mV. For example, if V_A is 2.7V_DC, ensure that −100mV ≤ input voltages ≤2.8V_DC to ensure accurate conversions.

(7) To ensure accuracy, it is required that V_A be well bypassed.

(8) Typical figures are at T_J = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level).

(9) This parameter is ensured by design and/or characterization and is not tested in production.

Figure 1. Input / Output Transfer Characteristic

Figure 2. Serial Timing Diagram

7.8 Typical Characteristics

f_SCLK = 30 MHz, T_A = 25°C, Input Code Range 12 to 1011, unless otherwise stated

Figure 3. DNL at V_A = 3 V

Figure 5. INL at V_A = 3 V

Figure 7. TUE at V_A = 3 V

Figure 9. DNL vs. V_A

Figure 11. 3-V DNL vs. f_SCLK

Figure 13. 3-V DNL vs. Clock Duty Cycle

Figure 15. 3-V DNL vs. Temperature

Figure 17. 3-V INL vs. f_SCLK

Figure 19. 3-V INL vs. Clock Duty Cycle

Figure 21. 3-V INL vs. Temperature

Figure 23. Zero Code Error vs. f_SCLK

Figure 25. Zero Code Error vs. Temperature

Figure 27. Full-Scale Error vs. Clock Duty Cycle

Figure 29. Supply Current vs. V_A

Figure 31. 5-V Glitch Response

Figure 33. 3-V Wake-Up Time

Figure 4. DNL at V_A = 5 V

Figure 6. INL at V_A = 5 V

Figure 8. TUE at V_A = 5 V

Figure 10. INL vs. V_A

Figure 12. 5-V DNL vs. f_SCLK

Figure 14. 5-V DNL vs. Clock Duty Cycle

Figure 16. 5-V DNL vs. Temperature

Figure 18. 5-V INL vs. f_SCLK

Figure 20. 5-V INL vs. Clock Duty Cycle

Figure 22. 5-V INL vs. Temperature

Figure 24. Zero Code Error vs. Clock Duty Cycle

Figure 26. Full-Scale Error vs. f_SCLK

Figure 28. Full-Scale Error vs. Temperature

Figure 30. Supply Current vs. Temperature

Figure 32. Power-On Reset

Figure 34. 5-V Wake-Up Time