The 20-bit DAC11001A, 18-bit DAC91001, and 16-bit DAC81001 (DACx1001) are highly accurate, low-noise, voltage-output, single-channel, digital-to-analog converters (DACs). The DACx1001 are specified monotonic by design, and offer excellent linearity of less than 4 LSB (max) across all ranges.
The unbuffered voltage output offers low noise performance (7 nV/√Hz) in combination with a fast settling time (1µs), making this device an excellent choice for low-noise, fast control-loop, and waveform generation applications. The DACx1001 integrates an enhanced deglitch circuit with code-independent ultra-low glitch (1 nV-s) to enable clean waveform ramps with ultra-low total harmonic distortion (THD).
The DACx1001 devices incorporate a power-on-reset circuit so that the DAC powers with known values in the registers. With external references, DAC output ranges from VREFPF to VREFNF can be achieved, including asymmetric output ranges.
The DACx1001 use a versatile 4–wire serial interface that operates at clock rates of up to 50 MHz. The DACx1001 is specified over the industrial temperature range of –40°C to +125°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DAC11001A | TQFP (48) | 7.00 mm × 7.00 mm |
DAC91001 | ||
DAC81001 |
Changes from A Revision (December 2019) to B Revision
Changes from * Revision (October 2019) to A Revision
DEVICE | RESOLUTION |
---|---|
DAC11001A | 20-bit |
DAC91001 | 18-bit |
DAC81001 | 16-bit |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | 2, 35, 38, 40, 42, 43, 46, 47 | Analog ground | Connect to 0 V. |
AGND-OUT | 8 | Analog ground | Connect to 0 V. Measure DAC output voltage with respect to this node. |
AGND-TnH | 14 | Analog ground | Connect to 0 V. Integrated deglitcher clock ground.. |
ALARM | 19 | Output | Alarm output |
AVDD | 39, 41 | Power | Positive low voltage analog power supply |
CLR | 30 | Input | DAC registers clear pin, active low |
DGND | 16, 17, 20, 21, 22, 23, 26 | Digital ground | Connect to 0 V. |
DVDD | 27 | Power | Digital power supply pin |
RFB | 9 | Input | Integrated precision resistor feedback node |
IOVDD | 28 | Power | Interface power supply pin |
LDAC | 18 | Input | Load DAC pin, active low |
NC | 1, 12, 13, 15, 24, 25, 29, 36, 37, 48 | — | No connection, leave floating |
OUT | 7 | Output | Unbuffered voltage output |
RCM | 11 | Input | Integrated precision resistor common-mode node |
REFNF | 5 | Input | External negative reference input. Connect to 0 V for unipolar DAC output. |
REFNS | 6 | Input | External negative reference sense node |
REFPF | 3 | Input | External positive reference input |
REFPS | 4 | Input | External positive reference sense node |
ROFS | 10 | Input | Integrated precision resistor offset node |
SCLK | 31 | Input | Serial clock input of serial peripheral interface (SPI). Schmitt-trigger logic input.
Data are transferred at rates of up to 50 MHz. |
SDIN | 32 | Input | Serial data input. Schmitt-trigger logic input.
Data are clocked into the input shift register on the falling edge of the serial clock input. |
SDO | 34 | Output | Serial data output. Data are valid on the falling edge of SCLK. |
SYNC | 33 | Input | SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless SYNC is low. When SYNC is high, the SDO pin is in high-impedance status. |
VCC | 45 | Power | Analog positive power supply |
VSS | 44 | Power | Analog negative power supply |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Positive supply voltage | AVDD to AGND | –0.3 | 7 | V | |
VCC to VSS | –0.3 | 40 | |||
VCC to AGND | –0.3 | 40 | |||
Negative supply voltage | VSS to AGND | –19 | 0.3 | V | |
Positive reference voltage | VREFPF to VREFNF | –0.3 | 40 | V | |
VREFPF to VCC | –0.3 | VCC + 0.3 | |||
VREFPF to AGND | –0.3 | 40 | |||
Negative reference voltage | VREFNF to AGND | –19 | 0.3 | V | |
VREFNF to VSS | VSS – 0.3 | 0.3 | |||
Digital and IO power supply | DVDD, IOVDD to DGND | –0.3 | 7 | V | |
Digital input(s) to DGND | DGND – 0.3 | IOVDD + 0.3 | V | ||
VOUT, VRFB, VRCM, VROFS | to AGND (VSS = AGND) | VSS | VCC | V | |
to VSS | 0 | VCC | |||
Alarm pin voltage, ALARM to DGND | –0.3 | DVDD + 0.3 | V | ||
Digital output, SDO to DGND | –0.3 | DVDD + 0.3 | V | ||
Current into any pin | –10 | 10 | mA | ||
TJ | Junction temperature | 150 | °C | ||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±1000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±250 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
AVDD to AGND | 4.5 | 5.5 | V | ||
VSS to AGND | –18 | –3 | V | ||
VCC to AGND | 8 | 33 | V | ||
VCC to VSS | 11 | 36 | V | ||
DVDD to DGND | 2.7 | 5.5 | V | ||
IOVDD to DGND | 1.7 | 5.5 | V | ||
AGND to DGND | –0.3 | 0.3 | V | ||
VIH digital input high voltage | 0.7 × IOVDD | V | |||
VIL digital input low voltage | 0.3 × IOVDD | V | |||
VREFPF to AGND | 3 | 15 | V | ||
VREFNF to AGND | –15 | 0 | V | ||
VREFPF to VREFNF | 3 | 30 | V | ||
TA | Operating temperature | –40 | 125 | °C |
THERMAL METRIC(1) | DAC11001A, DAC91001, DAC81001 | UNIT | |
---|---|---|---|
PFB (TQFP) | |||
48 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 51.0 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 10.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 16.2 | °C/W |
ΨJT | Junction-to-top characterization parameter | 0.3 | °C/W |
ΨJB | Junction-to-board characterization parameter | 16.0 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
STATIC PERFORMANCE | ||||||
Resolution | DAC11001A | 20 | Bits | |||
DAC91001 | 18 | |||||
DAC81001 | 16 | |||||
INL | Relative accuracy(2) | DAC11001A | –4 | 4 | LSB | |
DAC11001A(3)(4) | –2.6 | 2.6 | ||||
DAC11001A, TA = 25°C(4) | –2 | 2 | ||||
DAC91001 | –1 | 1 | ||||
DAC81001 | –1 | 1 | ||||
Relative accuracy drift over time(2) | TA = 25°C, 1000 hrs | ±0.1 | LSB | |||
DNL | Differential nonlinearity(2)(3) | –1 | 1 | LSB | ||
Zero code error(4) | DAC11001A, TA = 0°C to 70°C, code 0d into DAC, unipolar ranges only | –4 | 4 | LSB | ||
DAC11001A, TA = –40°C to +125°C, code 0d into DAC, unipolar ranges only | –4 | 4 | ||||
DAC11001A, TA = 25°C, unipolar ranges only | ±2 | |||||
DAC91001, TA = –40°C to +125°C, code 0d into DAC, unipolar ranges only | –4 | 4 | ||||
DAC81001, TA = –40°C to +125°C, code 0d into DAC, unipolar ranges only | –4 | 4 | ||||
Zero code error temperature coefficient | TA = 0°C to 70°C, code 0d into DAC, unipolar ranges only | ±0.04 | ppm FSR/°C | |||
TA = –40°C to +125°C, code 0d into DAC, unipolar ranges only | ±0.04 | |||||
Gain error(2)(4) | DAC11001A, TA = 0°C to 70°C | –8 | 8 | ppm of FSR | ||
DAC11001A, TA = 0°C to 70°C, VREFPF = 3 V, VREFNF = –10 V | –8 | 8 | ||||
DAC11001A, TA = –40°C to +125°C | –10 | 10 | ||||
DAC11001A, TA = 25°C | ±2 | |||||
DAC91001, TA = –40°C to +125°C | –10 | 10 | ||||
DAC81001, TA = –40°C to +125°C | –10 | 10 | ||||
Gain error temperature coefficient | TA = 0°C to 70°C | ±0.04 | ppm FSR/°C | |||
TA = 0°C to 70°C, VREFPF = 3 V, VREFNF = –10 V | ±0.04 | |||||
TA = –40°C to +125°C | ±0.04 | |||||
Positive full-scale error(4) | DAC11001A, TA = 0°C to 70°C, code 1048575d into DAC | –8 | 8 | LSB | ||
DAC11001A, TA = 0°C to 70°C, code 1048575d into DAC, VREFPF = 3 V, VREFNF = –10 V | –6 | 6 | ||||
DAC11001A, TA = –40°C to +125°C, code 1048575d into DAC | –10 | 10 | ||||
DAC11001A, TA = 25°C, code 1048575d into DAC | ±2 | |||||
DAC91001, TA = –40°C to +125°C, code 262143d into DAC | –10 | 10 | ||||
DAC81001, TA = –40°C to +125°C, code 65535d into DAC | –10 | 10 | ||||
Full-scale error temperature coefficient | TA = 0°C to 70°C | ±0.04 | ppm FSR/°C | |||
TA = 0°C to 70°C, VREFPF = 3 V, VREFNF = –10 V | ±0.04 | |||||
TA = –40°C to +125°C | ±0.04 | |||||
OUTPUT CHARACTERISTICS | ||||||
Headroom | From VREFPF to VCC | 3 | V | |||
Footroom | From VREFNF to VSS | 3 | V | |||
DC impedance | From ROFS to RCM | 5 | kΩ | |||
From RCM to RFB | 5 | |||||
ZO | DC output impedance | 2.5 | kΩ | |||
Power supply rejection ratio (dc) | TA = 25°C, VCC = 15 V ± 20%,
VSS = –15 V |
1.5 | µV/V | |||
TA = 25°C, VCC = 15 V,
VSS = –15 V ± 20% |
1 | |||||
Output voltage drift over time | TA = 25°C, VOUT = midscale, 1000 hr | 1 | ppm of FSR | |||
VOLTAGE REFERENCE INPUT | ||||||
Reference input impedance (REFPF) | DAC at midscale, VREFPF = 10 V, VREFNF = 0 V | 5.5 | kΩ | |||
Reference input impedance (REFNF) | DAC at midscale, VREFPF = 10 V, VREFNF = 0 V | 7 | ||||
DYNAMIC PERFORMANCE | ||||||
ts | Output voltage settling time(5) | VREFPF = 10 V, VREFNF = 0 V,
full-scale settling to 0.1%FSR |
1 | µs | ||
VREFPF = 10 V, VREFNF = 0 V,
full-scale settling to ±1 LSB |
2.5 | |||||
VREFPF = 10 V, VREFNF = 0 V,
1-mV step settling to ±1 LSB |
2.5 | |||||
SR | Slew rate | VREFPF = 10 V, VREFNF = 0 V, full-scale step, measured at OUT pin | 50 | V/µs | ||
Power-on glitch magnitude | Measured at unbuffered DAC voltage output, VREFPF = 10 V, VREFNF = 0 V | –0.2 | V | |||
Vn | Output noise | 0.1-Hz to 10-Hz, DAC at midscale, VREFPF = 10 V, VREFNF = 0 V | 0.4 | µVpp | ||
100-kHz bandwidth, DAC at midscale, VREFPF = 10 V, VREFNF = 0 V | 3 | µVrms | ||||
Output noise density | Measured at 1 kHz, 10 kHz, 100 kHz, DAC at mid scale, VREFPF = 10 V, VREFNF = 0 V | 7 | nV/√Hz | |||
SFDR | Spurious free dynamic range | DAC update rate = 400 kHz, fOUT = 1 kHz, VOUTPP = 0 V to 10 V | –105 | dB | ||
DAC update rate = 400 kHz, fOUT = 1 kHz, VOUTPP = 3 V to –10 V | –105 | dB | ||||
THD | Total harmonic distortion | DAC update rate = 400 kHz, fOUT = 1 kHz, VOUTPP = 0 V to 10 V | –105 | dB | ||
DAC update rate = 400 kHz, fOUT = 1 kHz, VOUTPP = 3 V to –10 V | –105 | dB | ||||
Power supply rejection ratio (ac) | 200-mV 50-Hz or 60-Hz sine wave superimposed on VSS, VCC = 15 V | 95 | dB | |||
200-mV 50 Hz or 60 Hz sine wave superimposed on VCC, VSS = –15 V | 95 | dB | ||||
Code change glitch impulse | ±1 LSB change around mid code (including feedthrough), VREFPF = 10 V, VREFNF = 0 V, measured at output of buffer op amp | 1 | nV-s | |||
Code change glitch impulse magnitude | ±1 LSB change around mid code (including feedthrough), VREFPF = 10 V, VREFNF = 0 V, measured at output of buffer op amp | 5 | mV | |||
Reference feedthrough | VREFPF = 10 V ± 10%, VREFNF = 0 V, frequency = 100 Hz, DAC at zero scale | –90 | dB | |||
Reference feedthrough | VREFNF = –10 V ± 10%, VREFPF = 10 V, frequency = 100 Hz, DAC at full scale | –90 | dB | |||
Digital feedthrough | At SCLK = 1 MHz, DAC output static at midscale, 10-V range | 1 | nV-s | |||
DIGITAL INPUTS | ||||||
Hysteresis voltage | 0.4 | V | ||||
Input current | ±5 | µA | ||||
Pin capacitance | Per pin | 10 | pF | |||
DIGITAL OUTPUTS | ||||||
VOL | Output low voltage | sinking 200 µA | 0.4 | V | ||
VOH | Output high voltage | sourcing 200 µA | IOVDD – 0.5 | V | ||
High impedance leakage | ±5 | µA | ||||
High impedance output capacitance | 10 | pF | ||||
POWER | ||||||
IAVDD | Current flowing into AVDD | VREFPF = 10 V, VREFNF = 0 V, midscale code | 1.5 | mA | ||
IVCC | Current flowing into VCC | VREFPF = 10 V, VREFNF = 0 V, midscale code | 7 | mA | ||
IVSS | Current flowing into VSS | VREFPF = 10 V, VREFNF = 0 V, midscale code | 7 | mA | ||
IDVDD | Current flowing into DVDD | VREFPF = 10 V, VREFNF = 0 V, midscale code | 0.5 | mA | ||
IIOVDD | Current flowing into IOVDD | VREFPF = 10 V, VREFNF = 0 V, midscale code, all digital input pins static at IOVDD | 0.1 | mA | ||
IREFPF | Reference input current (VREFPF) | VREFPF = 10 V, VREFNF = 0 V, midscale code | 5 | mA | ||
IREFNF | Reference input current (VREFNF) | VREFPF = 10 V, VREFNF = 0 V, midscale code | 5 | mA |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCLK frequency, 1.7 V ≤ IOVDD < 2.7 V | 33 | MHz | ||
SCLK frequency, 2.7 V ≤ IOVDD ≤ 5.5 V | 50 | ||||
tSCLKHIGH | SCLK high time, 1.7 V ≤ IOVDD < 2.7 V | 15 | ns | ||
SCLK high time, 2.7 V ≤ IOVDD ≤ 5.5 V | 10 | ||||
tSCLKLOW | SCLK low time, 1.7 V ≤ IOVDD < 2.7 V | 15 | ns | ||
SCLK low time, 2.7 V ≤ IOVDD ≤ 5.5 V | 10 | ||||
tSDIS | SDI setup, 1.7 V ≤ IOVDD < 2.7 V | 13 | ns | ||
SDI setup, 2.7 V ≤ IOVDD ≤ 5.5 V | 8 | ||||
tSDIH | SDI hold, 1.7 V ≤ IOVDD < 2.7 V | 13 | ns | ||
SDI hold, 2.7 V ≤ IOVDD ≤ 5.5 V | 8 | ||||
tCSS | SYNC falling edge to SCLK falling edge, 1.7 V ≤ IOVDD < 2.7 V | 23 | ns | ||
SYNC falling edge to SCLK falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V | 18 | ||||
tCSH | SCLK falling edge to SYNC rising edge, 1.7 V ≤ IOVDD < 2.7 V | 15 | ns | ||
SCLK falling edge to SYNC rising edge, 2.7 V ≤ IOVDD ≤ 5.5 V | 10 | ||||
tCSHIGH | SYNC high time, 1.7 V ≤ IOVDD < 2.7 V | 55 | ns | ||
SYNC high time, 2.7 V ≤ IOVDD ≤ 5.5 V | 50 | ||||
tCSIGNORE | SCLK falling edge to SYNC ignore, 1.7 V ≤ IOVDD < 2.7 V | 10 | ns | ||
SCLK falling edge to SYNC ignore, 2.7 V ≤ IOVDD ≤ 5.5 V | 5 | ||||
tLDACSL | Synchronous update: SYNC rising edge to LDAC falling edge, 1.7 V ≤ IOVDD < 2.7 V | 50 | ns | ||
Synchronous update: SYNC rising edge to LDAC falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V | 50 | ||||
tLDACW | LDAC low time, 1.7 V ≤ IOVDD < 2.7 V | 20 | ns | ||
LDAC low time, 2.7 V ≤ IOVDD ≤ 5.5 V | 20 | ||||
tCLRW | CLR low time, 1.7 V ≤ IOVDD < 2.7 V | 20 | ns | ||
CLR low time, 2.7 V ≤ IOVDD ≤ 5.5 V | 20 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCLK frequency, 1.7 V ≤ IOVDD < 2.7 V | 20 | MHz | ||
SCLK frequency, 2.7 V ≤ IOVDD ≤ 5.5 V | 25 | ||||
tSCLKHIGH | SCLK high time, 1.7 V ≤ IOVDD < 2.7 V | 25 | ns | ||
SCLK high time, 2.7 V ≤ IOVDD ≤ 5.5 V | 20 | ||||
tSCLKLOW | SCLK low time, 1.7 V ≤ IOVDD < 2.7 V | 25 | ns | ||
SCLK low time, 2.7 V ≤ IOVDD ≤ 5.5 V | 20 | ||||
tSDIS | SDI setup, 1.7 V ≤ IOVDD < 2.7 V | 21 | ns | ||
SDI setup, 2.7 V ≤ IOVDD ≤ 5.5 V | 16 | ||||
tSDIH | SDI hold, 1.7 V ≤ IOVDD < 2.7 V | 21 | ns | ||
SDI hold, 2.7 V ≤ IOVDD ≤ 5.5 V | 16 | ||||
tCSS | SYNC falling edge to SCLK falling edge, 1.7 V ≤ IOVDD < 2.7 V | 41 | ns | ||
SYNC falling edge to SCLK falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V | 36 | ||||
tCSH | SCLK falling edge to SYNC rising edge, 1.7 V ≤ IOVDD < 2.7 V | 25 | ns | ||
SCLK falling edge to SYNC rising edge, 2.7 V ≤ IOVDD ≤ 5.5 V | 20 | ||||
tCSHIGH | SYNC high time, 1.7 V ≤ IOVDD < 2.7 V | 100 | ns | ||
SYNC high time, 2.7 V ≤ IOVDD ≤ 5.5 V | 100 | ||||
tCSIGNORE | SCLK falling edge to SYNC ignore, 1.7 V ≤ IOVDD < 2.7 V | 10 | ns | ||
SCLK falling edge to SYNC ignore, 2.7 V ≤ IOVDD ≤ 5.5 V | 5 | ||||
tLDACSL | Synchronous update: SYNC rising edge to LDAC falling edge, 1.7 V ≤ IOVDD < 2.7 V | 100 | ns | ||
Synchronous update: SYNC rising edge to LDAC falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V | 100 | ||||
tLDACW | LDAC low time, 1.7 V ≤ IOVDD < 2.7 V | 40 | ns | ||
LDAC low time, 2.7 V ≤ IOVDD ≤ 5.5 V | 40 | ||||
tCLRW | CLR low time, 1.7 V ≤ IOVDD < 2.7 V | 40 | ns | ||
CLR low time, 2.7 V ≤ IOVDD ≤ 5.5 V | 40 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
fSCLK | SCLK frequency | 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 | 10 | MHz | ||
1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 | 20 | |||||
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 | 15 | |||||
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 | 30 | |||||
tSCLKHIGH | SCLK high time | 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 | 50 | ns | ||
1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 | 25 | |||||
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 | 33 | |||||
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 | 16 | |||||
tSCLKLOW | SCLK low time | 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 | 50 | ns | ||
1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 | 25 | |||||
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 | 33 | |||||
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 | 16 | |||||
tSDIS | SDI setup, 1.7 V ≤ IOVDD < 2.7 V | 13 | ns | |||
SDI setup, 2.7 V ≤ IOVDD ≤ 5.5 V | 8 | |||||
tSDIH | SDI hold, 1.7 V ≤ IOVDD < 2.7 V | 13 | ns | |||
SDI hold, 2.7 V ≤ IOVDD ≤ 5.5 V | 8 | |||||
tCSS | SYNC falling edge to SCLK falling edge, 1.7 V ≤ IOVDD < 2.7 V | 30 | ns | |||
SYNC falling edge to SCLK falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V | 20 | |||||
tCSH | SCLK falling edge to SYNC rising edge, 1.7 V ≤ IOVDD < 2.7 V | 15 | ns | |||
SCLK falling edge to SYNC rising edge, 2.7 V ≤ IOVDD ≤ 5.5 V | 10 | |||||
tCSHIGH | SYNC high time, 1.7 V ≤ IOVDD < 2.7 V | 55 | ns | |||
SYNC high time, 2.7 V ≤ IOVDD ≤ 5.5 V | 50 | |||||
tCSIGNORE | SCLK falling edge to SYNC ignore, 1.7 V ≤ IOVDD < 2.7 V | 10 | ns | |||
SCLK falling edge to SYNC ignore, 2.7 V ≤ IOVDD ≤ 5.5 V | 5 | |||||
tLDACSL | Synchronous update: SYNC rising edge to LDAC falling edge, 1.7 V ≤ IOVDD < 2.7 V | 50 | ns | |||
Synchronous update: SYNC rising edge to LDAC falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V | 50 | |||||
tLDACW | LDAC low time, 1.7 V ≤ IOVDD < 2.7 V | 20 | ns | |||
LDAC low time, 2.7 V ≤ IOVDD ≤ 5.5 V | 20 | |||||
tCLRW | CLR low time, 1.7 V ≤ IOVDD < 2.7 V | 20 | ns | |||
CLR low time, 2.7 V ≤ IOVDD ≤ 5.5 V | 20 | |||||
tSDODLY | SCLK rising edge to SDO valid data, 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 | 0 | 35 | ns | ||
SCLK rising edge to SDO valid data, 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 | 0 | 25 | ||||
SCLK falling edge to SDO valid data, 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 | 0 | 35 | ||||
SCLK falling edge to SDO valid data, 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 | 0 | 25 | ||||
tSDOZ | SYNC rising edge to SDO HiZ, 1.7 V ≤ IOVDD < 2.7 V | 0 | 20 | ns | ||
SYNC rising edge to SDO HiZ, 2.7 V ≤ IOVDD ≤ 5.5 V | 0 | 20 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
fSCLK | SCLK frequency | 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 | 8 | MHz | ||
1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 | 16 | |||||
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 | 10 | |||||
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 | 20 | |||||
tSCLKHIGH | SCLK high time | 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 | 62 | ns | ||
1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 | 31 | |||||
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 | 50 | |||||
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 | 25 | |||||
tSCLKLOW | SCLK low time | 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 | 62 | ns | ||
1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 | 31 | |||||
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 | 50 | |||||
2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 | 25 | |||||
tSDIS | SDI setup, 1.7 V ≤ IOVDD < 2.7 V | 21 | ns | |||
SDI setup, 2.7 V ≤ IOVDD ≤ 5.5 V | 16 | |||||
tSDIH | SDI hold, 1.7 V ≤ IOVDD < 2.7 V | 21 | ns | |||
SDI hold, 2.7 V ≤ IOVDD ≤ 5.5 V | 16 | |||||
tCSS | SYNC falling edge to SCLK falling edge, 1.7 V ≤ IOVDD < 2.7 V | 41 | ns | |||
SYNC falling edge to SCLK falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V | 36 | |||||
tCSH | SCLK falling edge to SYNC rising edge, 1.7 V ≤ IOVDD < 2.7 V | 25 | ns | |||
SCLK falling edge to SYNC rising edge, 2.7 V ≤ IOVDD ≤ 5.5 V | 20 | |||||
tCSHIGH | SYNC high time, 1.7 V ≤ IOVDD < 2.7 V | 100 | ns | |||
SYNC high time, 2.7 V ≤ IOVDD ≤ 5.5 V | 100 | |||||
tCSIGNORE | SCLK falling edge to SYNC ignore, 1.7 V ≤ IOVDD < 2.7 V | 10 | ns | |||
SCLK falling edge to SYNC ignore, 2.7 V ≤ IOVDD ≤ 5.5 V | 5 | |||||
tLDACSL | Synchronous update: SYNC rising edge to LDAC falling edge, 1.7 V ≤ IOVDD < 2.7 V | 100 | ns | |||
Synchronous update: SYNC rising edge to LDAC falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V | 100 | |||||
tLDACW | LDAC low time, 1.7 V ≤ IOVDD < 2.7 V | 40 | ns | |||
LDAC low time, 2.7 V ≤ IOVDD ≤ 5.5 V | 40 | |||||
tCLRW | CLR low time, 1.7 V ≤ IOVDD < 2.7 V | 40 | ns | |||
CLR low time, 2.7 V ≤ IOVDD ≤ 5.5 V | 40 | |||||
tSDODLY | SCLK rising edge to SDO valid data, 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 | 0 | 40 | ns | ||
SCLK rising edge to SDO valid data, 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 | 0 | 30 | ||||
SCLK rising edge to SDO valid data, 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 | 0 | 40 | ||||
SCLK rising edge to SDO valid data, 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 | 0 | 30 | ||||
tSDOZ | SYNC rising edge to SDO HiZ, 1.7 V ≤ IOVDD < 2.7 V | 0 | 20 | ns | ||
SYNC rising edge to SDO HiZ, 2.7 V ≤ IOVDD ≤ 5.5 V | 0 | 20 |
VREFPF = 10 V, VREFNF = 0 V |
VREFPF = 10 V, VREFNF = 0 V |
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode |
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode |
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode |
VREFPF = 10 V, VREFNF = –10 V, DAC transition midcode – 1 to midcode |
VREFPF = 10 V, VREFNF = –10 V |
VREFPF = 5 V, VREFNF = 0 V |
VREFPF = 10 V, VREFNF = 0 V | ||
VREFPF = 10 V, VREFNF = 0 V, DAC transitions 100 codes around midscale |
VREFPF = 10 V, VREFNF = 0 V, measured at DAC output |
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode, measured at DAC output pin |
VREFPF = 10 V, VREFNF = 0 V |
VREFPF = 10 V, VREFNF = 0 V |
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode |
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode |
VREFPF = 5 V, VREFNF = 0 V, DAC at midcode |
VREFPF = 10 V, VREFNF = 0 V, DAC at midcode |
VREFPF = 10 V, VREFNF = –10 V, DAC transition midcode to midcode – 1 |
VREFPF = 10 V, VREFNF = 0 V |
VREFPF = 10 V, VREFNF = 0 V | ||
VREFPF = 10 V, VREFNF = 0 V, DAC transitions 100 codes around midscale |
VREFPF = 10 V, VREFNF = 0 V, DAC output frequency = 1 kHz, DAC update rate = 400 kHz |