SBAS649B June 2021 – June 2022 DAC12DL3200
PRODUCTION DATA
The design operates in 2nd Nyquist zone for the DAC and ADC with a sample rate of 3.2 GSPS (3.2 GHz clock). The DAC is used in RF mode to enhance 2nd Nyquist zone output power. A frequency range of 2.0 to 2.8 GHz is reasonable for design of the Nyquist filter at the ADC input.
The ADC and DAC use the same LMK04828 clock source, which is important for cancellation of the clock phase noise between the ADC input and DAC output. A Xilinx XCKU060 Kintex® UltraScale™ FPGA is used for the FPGA to loopback data from the ADC12DL3200 to DAC12DL3200. No signal processing is included in the FPGA firmware, as that is beyond the scope of this example.