7.4.1 Synchronization Modes
There are three modes of syncing included in the DAC31x1: NORMAL Dual Sync, SYNC ONLY, and SIF_SYNC.
- NORMAL Dual Sync: The SYNC pin is used to align the input side of the FIFO (write pointers) with the A(0) sample. The ALIGN pin is used to reset the output side of the FIFO (read pointers) to the offset value. Multiple chip alignment can be accomplished with this kind of syncing.
- SYNC ONLY: In this mode only the SYNC pin is used to sync both the read and write pointers of the FIFO. There is an asynchronized handoff between the DATACLK and DACCLK when using this mode therefore, it is impossible to accurately align multiple chips closer than 2 T or 3 T.
- SIF_SYNC: When neither SYNC nor ALIGN are used, a programmable SYNC pulse can be used to sync the design. However, the same issues as ISTROBE ONLY apply. There is an asynchronized handoff between the serial clock domain and the two sides of the FIFO. As a result of of the asynchronous nature of the SIF_SYNC, it is impossible to align the sync up with any sample at the input. SIF_SYNC mode is the only synchronisation mode supported in the 7-bit interface mode.
NOTE
When ALIGNP or ALIGNN is not used, TI recommends clearing the alignrx_ena register (config1, bit 4), and tie ALIGNP to DIGVDD18 and ALIGNN to GROUND. When SYNCP or SYNCN is not used, clear the register lvdssyncrx_ena (config0, bit3), and the unused SYNCP or SYNCN pins can be left open or tied to GROUND.