CONTROL AND SERIAL |
ALARM |
47 |
O |
CMOS output for ALARM condition. |
RESETB |
41 |
I |
Serial interface reset input, active low. Initialized internal registers during high-to-low transition. Asynchronous. Internal pullup. A reset event after every power cycle may be required to reinitialize all SPI registers to default values. |
SCLK |
43 |
I |
Serial interface clock. Internal pulldown. |
SDENB |
42 |
I |
Serial data enable. Internal pullup. |
SDIO |
44 |
I/O |
Bidirectional serial data in 3-pin mode (default). In 4-pin interface mode (sif4_ena [config0, bit 9]), the SDIO pin in an input only. Internal pulldown. |
SDO |
46 |
O |
Unidirectional serial interface data in 4-pin mode (sif4_ena [config0, bit 9]). The SDO pin is made high impedance in 3-pin interface mode (default). Internal pulldown. |
SLEEP |
49 |
I |
Puts device in sleep, active high. Internal pulldown. |
TXENABLE |
48 |
I |
Transmit enable, active high input. TXENABLE must be high for the data to the DAC to be enabled. When TXENABLE is low, the digital logic section is forced to all 0, and any input data are ignored. Internal pulldown. |
DATA INTERFACE |
ALIGNN |
5 |
I |
LVPECL FIFO output synchronization. This positive or negative pair is captured with the rising edge of DACCLKx. This pin is used to reset the clock dividers and for multiple DAC synchronization. If unused, this pin can be left unconnected. |
ALIGNP |
4 |
I |
DATA[13:0]N |
10, 12, 14, 16, 18, 20, 23, 27, 30, 32, 34, 36, 38, 40 |
I |
LVDS input data bits for both channels. Each positive and negative LVDS pair has an internal 100-Ω termination resistor. Data format relative to DATACLKx clock is dual data rate (DDR) with two data transfers per DATACLKx clock cycles.
The data format is interleaved with channel A (rising edge) and channel B (falling edge).
In the default mode (reverse bus not enabled):
DATA13x is most significant data bit (MSB)
DATA0x is least significant data bit (LSB)
|
DATA[13:0]P |
9, 11, 13, 15, 17, 19, 22, 26, 29, 31, 33, 35, 37, 39 |
I |
DATACLKN |
25 |
I |
DDR differential input data clock. Edge to center nominal timing. Ch A rising edge, Ch B falling edge in multiplexed output mode. |
DATACLKP |
24 |
I |
SYNCN |
7 |
I |
This pin resets the FIFO or is used as a syncing source. These two functions are captured with the rising edge of DATACLKx. The signal captured by the falling edge of DATACLKx. |
SYNCP |
6 |
I |
OUTPUT AND CLOCK |
DACCLKN |
2 |
I |
LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18 / 2. |
DACCLKP |
1 |
I |
IOUTAN |
60 |
O |
A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full-scale current source, and the most positive voltage on the IOUTAP pin. Similarly, a 0xFFFF data input results in a 0-mA current source, and the least positive voltage on the IOUTAP pin. The IOUTAN pin is the complement of IOUTAP. |
IOUTAP |
61 |
O |
IOUTBN |
54 |
O |
B-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full-scale current source, and the most positive voltage on the IOUTBP pin. Similarly, a 0xFFFF data input results in a 0-mA current source, and the least positive voltage on the IOUTBP pin. The IOUTBN pin is the complement of IOUTBP. |
IOUTBP |
53 |
O |
REFERENCE |
BIASJ |
57 |
O |
Full-scale output current bias. For 20-mA full-scale output current, connect a 960-Ω resistor to GND. |
EXTIO |
58 |
I/O |
Used as external reference input when internal reference is disabled. Requires a 0.1-µF decoupling capacitor to GND when used as reference output. |
POWER SUPPLY |
CLKVDD18 |
3 |
I |
1.8-V clock supply. |
DIGVDD18 |
21, 28 |
I |
1.8-V digital supply. Also supplies LVDS receivers. |
IOVDD |
45 |
I |
Supply voltage for CMOS I/Os. 1.8 V to 3.3 V. |
VDDA18 |
50, 64 |
I |
Analog 1.8-V supply. |
VDDA33 |
55, 56, 59 |
I |
Analog 3.3-V supply. |
VFUSE |
8 |
I |
Digital supply voltage (1.8 V). This supply pin is also used for factory fuse programming. Connect to DVDD pins for normal operation. |
NC |
51, 52, 62, 63 |
— |
Not used. These pins can be left open or tied to ground in actual application use. |
GND PAD |
— |
— |
This thermal pad is the electrical ground connection for the device (backside). |