SLAS646C December   2009  – May 2015 DAC3282

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - DC Specifications
    6. 6.6 Electrical Characteristics - AC Specifications
    7. 6.7 Electrical Characteristics - Digital Specifications
    8. 6.8 Timing Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input FIFO
      2. 7.3.2  FIFO Alarms
      3. 7.3.3  FIFO Modes of Operation
      4. 7.3.4  Dual Sync Sources Mode
      5. 7.3.5  Single Sync Source Mode
      6. 7.3.6  Bypass Mode
      7. 7.3.7  Data Pattern Checker
      8. 7.3.8  FIR Filters
      9. 7.3.9  Coarse Mixer
      10. 7.3.10 Digital Offset Control
      11. 7.3.11 Temperature Sensor
      12. 7.3.12 Sleep Modes
      13. 7.3.13 Reference Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Data Interface
      2. 7.4.2 LVPECL Inputs
      3. 7.4.3 LVDS Inputs
      4. 7.4.4 CMOS Digital Inputs
      5. 7.4.5 DAC Transfer Function
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
    6. 7.6 Register Maps
      1. 7.6.1  CONFIG0 (address = 0x00) [reset = 0x70]
      2. 7.6.2  CONFIG1 (address = 0x01) [reset = 0x11]
      3. 7.6.3  CONFIG2 (address = 0x02) [reset = 0x00]
      4. 7.6.4  CONFIG3 (address = 0x03) [reset = 0x10]
      5. 7.6.5  CONFIG4 (address = 0x04) [reset = 0xFF]
      6. 7.6.6  CONFIG5 (address = 0x05) READ ONLY
      7. 7.6.7  CONFIG6 (address =0x06) [reset = 0x00]
      8. 7.6.8  CONFIG7 (address = 0x07) [reset = 0x00] (WRITE TO CLEAR)
      9. 7.6.9  CONFIG8 (address = 0x08) [reset = 0x00] (WRITE TO CLEAR)
      10. 7.6.10 CONFIG9 (address = 0x09) [reset = 0x7A]
      11. 7.6.11 CONFIG10 (address = 0x0A) [reset = 0xB6]
      12. 7.6.12 CONFIG11 (address = 0x0B) [reset = 0xEA]
      13. 7.6.13 CONFIG12 (address =0x0C) [reset = 0x45]
      14. 7.6.14 CONFIG13 (address =0x0D) [reset = 0x1A]
      15. 7.6.15 CONFIG14 Register Name (address = 0x0E) [reset = 0x16]
      16. 7.6.16 CONFIG15 Register Name (address = 0x0F) [reset = 0xAA]
      17. 7.6.17 CONFIG16 (address = 0x10) [reset = 0xC6]
      18. 7.6.18 CONFIG17 (address = 0x11) [reset = 0x00]
      19. 7.6.19 CONFIG18 (address = 0x12) [reset = 0x02]
      20. 7.6.20 CONFIG19 (address = 0x13) [reset = 0x00]
      21. 7.6.21 CONFIG20 (address = 0x14) [reset = 0x00] (CAUSES AUTOSYNC)
      22. 7.6.22 CONFIG21 (address = 0x15) [reset = 0x00]
      23. 7.6.23 CONFIG22 (address = 0x16) [reset = 0x00]
      24. 7.6.24 CONFIG23 (address = 0x17) [reset = 0x00]
      25. 7.6.25 CONFIG24 (address = 0x18) [reset = 0x83]
      26. 7.6.26 CONFIG25 (address = 0x19) [reset = 0x00]
      27. 7.6.27 CONFIG26 (address = 0x1A) [reset = 0x00]
      28. 7.6.28 CONFIG27 (address =0x1B) [reset = 0x00]
      29. 7.6.29 CONFIG28 (address = 0x1C) [reset = 0x00]
      30. 7.6.30 CONFIG29 (address = 0x1D) [reset = 0x00]
      31. 7.6.31 CONFIG30 (address = 0x1E) [reset = 0x00]
      32. 7.6.32 VERSION31 (address = 0x1F) [reset = 0x43] (READ ONLY)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multi-device Synchronization
        1. 8.1.1.1 Multi-device Synchronization: Dual Sync Sources Mode
        2. 8.1.1.2 Multi-device Operation: Single Sync Source Mode
      2. 8.1.2 Analog Current Outputs
      3. 8.1.3 Passive Interface to Analog Quadrature Modulators
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power-up Sequence
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Definition Of Specifications
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Device and Documentation Support

11.1 Device Support

11.1.1 Definition Of Specifications

Adjacent Carrier Leakage Ratio (ACLR) Defined for a 3.84 Mcps 3GPP W-CDMA input signal measured in a 3.84 MHz bandwidth at a 5MHz offset from the carrier with a 12 dB peak-to-average ratio.
Analog and Digital Power Supply Rejection Ratio (APSSR, DPSSR) Defined as the percentage error in the ratio of the delta IOUT and delta supply voltage normalized with respect to the ideal IOUT current.
Differential Nonlinearity (DNL) Defined as the variation in analog output associated with an ideal 1 LSB change in the digital input code.
Gain Drift Defined as the maximum change in gain, in terms of ppm of full-scale range (FSR) per °C, from the value at ambient (25°C) to values over the full operating temperature range.
Gain Error Defined as the percentage error (in FSR%) for the ratio between the measured full-scale output current and the ideal full-scale output current.
Integral Nonlinearity (INL) Defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale.
Intermodulation Distortion
(IMD3, IMD)		 The two-tone IMD3 is defined as the ratio (in dBc) of the 3rd-order intermodulation distortion product to either fundamental output tone.
Noise Spectral Density (NSD) Defined as the difference of power (in dBc) between the output tone signal power and the noise floor of 1Hz bandwidth within the first Nyquist zone.
Offset Drift Defined as the maximum change in DC offset, in terms of ppm of full-scale range (FSR) per °C, from the value at ambient (25°C) to values over the full operating temperature range.
Offset Error Defined as the percentage error (in FSR%) for the ratio between the measured mid-scale output current and the ideal mid-scale output current.
Output Compliance Range Defined as the minimum and maximum allowable voltage at the output of the current-output DAC. Exceeding this limit may result reduced reliability of the device or adversely affecting distortion performance.
Reference Voltage Drift Defined as the maximum change of the reference voltage in ppm per °C from value at ambient (25°C) to values over the full operating temperature range.
Spurious Free Dynamic Range (SFDR) Defined as the difference (in dBc) between the peak amplitude of the output signal and the peak spurious signal.

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.3 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.