SLAS748G March   2011  – January 2024 DAC3482

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics – DC Specifications
    6. 5.6  Electrical Characteristics – Digital Specifications
    7. 5.7  Electrical Characteristics – AC Specifications
    8. 5.8  Electrical Characteristics - Phase-Locked Loop Specifications
    9. 5.9  Timing Requirements - Digital Specifications
    10. 5.10 Switching Characteristics – AC Specifications
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Serial Interface
      2. 6.3.2  Data Interface
        1. 6.3.2.1 Word-Wide Format
        2. 6.3.2.2 Byte-Wide Format
      3. 6.3.3  Input FIFO
      4. 6.3.4  FIFO Modes of Operation
        1. 6.3.4.1 Dual Sync Source Mode
        2. 6.3.4.2 Single Sync Source Mode
        3. 6.3.4.3 Bypass Mode
      5. 6.3.5  Clocking Modes
        1. 6.3.5.1 PLL Bypass Mode
        2. 6.3.5.2 PLL Mode
      6. 6.3.6  FIR Filters
      7. 6.3.7  Complex Signal Mixer
        1. 6.3.7.1 Full Complex Mixer
        2. 6.3.7.2 Coarse Complex Mixer
        3. 6.3.7.3 Mixer Gain
        4. 6.3.7.4 Real Channel Upconversion
      8. 6.3.8  Quadrature Modulation Correction (QMC)
        1. 6.3.8.1 Gain and Phase Correction
        2. 6.3.8.2 Offset Correction
        3. 6.3.8.3 Group Delay Correction
      9. 6.3.9  Temperature Sensor
      10. 6.3.10 Data Pattern Checker
      11. 6.3.11 Parity Check Test
        1. 6.3.11.1 Word-by-Word Parity
        2. 6.3.11.2 Block Parity
      12. 6.3.12 DAC3482 Alarm Monitoring
      13. 6.3.13 LVPECL Inputs
      14. 6.3.14 LVDS Inputs
      15. 6.3.15 Unused LVDS Port Termination
      16. 6.3.16 CMOS Digital Inputs
      17. 6.3.17 Reference Operation
      18. 6.3.18 DAC Transfer Function
      19. 6.3.19 Analog Current Outputs
    4. 6.4 Device Functional Modes
      1. 6.4.1 Multi-Device Synchronization
        1. 6.4.1.1 Multi-Device Synchronization: PLL Bypassed with Dual Sync Sources Mode
        2. 6.4.1.2 Multi-Device Synchronization: PLL Enabled with Dual Sync Sources Mode
        3. 6.4.1.3 Multi-Device Operation: Single Sync Source Mode
    5. 6.5 Programming
      1. 6.5.1 Power-Up Sequence
      2. 6.5.2 Example Start-Up Routine
        1. 6.5.2.1 Device Configuration
        2. 6.5.2.2 PLL Configuration
        3. 6.5.2.3 NCO Configuration
        4. 6.5.2.4 Example Start-Up Sequence
    6. 6.6 Register Map
      1. 6.6.1 Register Descriptions
        1. 6.6.1.1  Register Name: config0 – Address: 0x00, Default: 0x049C
        2. 6.6.1.2  Register Name: config1 – Address: 0x01, Default: 0x050E
        3. 6.6.1.3  Register Name: config2 – Address: 0x02, Default: 0x7000
        4. 6.6.1.4  Register Name: config3 – Address: 0x03, Default: 0xF000
        5. 6.6.1.5  Register Name: config4 – Address: 0x04, Default: No RESET Value (WRITE TO CLEAR)
        6. 6.6.1.6  Register Name: config5 – Address: 0x05, Default: Setup and Power-Up Conditions Dependent (WRITE TO CLEAR)
        7. 6.6.1.7  Register Name: config6 – Address: 0x06, Default: No RESET Value (READ ONLY)
        8. 6.6.1.8  Register Name: config7 – Address: 0x07, Default: 0xFFFF
        9. 6.6.1.9  Register Name: config8 – Address: 0x08, Default: 0x0000 (CAUSES AUTO-SYNC)
        10. 6.6.1.10 Register Name: config9 – Address: 0x09, Default: 0x8000
        11. 6.6.1.11 Register Name: config10 – Address: 0x0A, Default: 0x0000
        12. 6.6.1.12 Register Name: config11 – Address: 0x0B, Default: 0x0000
        13. 6.6.1.13 Register Name: config12 – Address: 0x0C, Default: 0x0400
        14. 6.6.1.14 Register Name: config13 – Address: 0x0D, Default: 0x0400
        15. 6.6.1.15 Register Name: config14 – Address: 0x0E, Default: 0x0400
        16. 6.6.1.16 Register Name: config15 – Address: 0x0F, Default: 0x0400
        17. 6.6.1.17 Register Name: config16 – Address: 0x10, Default: 0x0000 (CAUSES AUTO-SYNC)
        18. 6.6.1.18 Register Name: config17 – Address: 0x11, Default: 0x0000
        19. 6.6.1.19 Register Name: config18 – Address: 0x12, Default: 0x0000 (CAUSES AUTO-SYNC)
        20. 6.6.1.20 Register Name: config19 – Address: 0x13, Default: 0x0000
        21. 6.6.1.21 Register Name: config20 – Address: 0x14, Default: 0x0000
        22. 6.6.1.22 Register Name: config21 – Address: 0x15, Default: 0x0000
        23. 6.6.1.23 Register name: config22 – Address: 0x16, Default: 0x0000
        24. 6.6.1.24 Register Name: config23 – Address: 0x17, Default: 0x0000
        25. 6.6.1.25 Register Name: config24 – Address: 0x18, Default: NA
        26. 6.6.1.26 Register Name: config25 – Address: 0x19, Default: 0x0440
        27. 6.6.1.27 Register Name: config26 – Address: 0x1A, Default: 0x0020
        28. 6.6.1.28 Register Name: config27 – Address: 0x1B, Default: 0x0000
        29. 6.6.1.29 Register Name: config28 – Address: 0x1C, Default: 0x0000
        30. 6.6.1.30 Register Name: config29 – Address: 0x1D, Default: 0x0000
        31. 6.6.1.31 Register Name: config30 – Address: 0x1E, Default: 0x1111
        32. 6.6.1.32 Register Name: config31 – Address: 0x1F, Default: 0x1140
        33. 6.6.1.33 Register Name: config32 – Address: 0x20, Default: 0x2400
        34. 6.6.1.34 Register Name: config33 – Address: 0x21, Default: 0x0000
        35. 6.6.1.35 Register Name: config34 – Address: 0x22, Default: 0x1B1B
        36. 6.6.1.36 Register Name: config35 – Address: 0x23, Default: 0xFFFF
        37. 6.6.1.37 Register Name: config36 – Address: 0x24, Default: 0x0000
        38. 6.6.1.38 Register Name: config37 – Address: 0x25, Default: 0x7A7A
        39. 6.6.1.39 Register Name: config38 – Address: 0x26, Default: 0xB6B6
        40. 6.6.1.40 Register Name: config39 – Address: 0x27, Default: 0xEAEA
        41. 6.6.1.41 Register Name: config40 – Address: 0x28, Default: 0x4545
        42. 6.6.1.42 Register Name: config41 – Address: 0x29, Default: 0x1A1A
        43. 6.6.1.43 Register Name: config42 – Address: 0x2A, Default: 0x1616
        44. 6.6.1.44 Register Name: config43 – Address: 0x2B, Default: 0xAAAA
        45. 6.6.1.45 Register Name: config44 – Address: 0x2C, Default: 0xC6C6
        46. 6.6.1.46 Register Name: config45 – Address: 0x2D, Default: 0x0004
        47. 6.6.1.47 Register Name: config46 – Address: 0x2E, Default: 0x0000
        48. 6.6.1.48 Register Name: config47 – Address: 0x2F, Default: 0x0000
        49. 6.6.1.49 Register Name: config48 – Address: 0x30, Default: 0x0000
        50. 6.6.1.50 Register Name: version– Address: 0x7F, Default: 0x540C (READ ONLY)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 IF Based LTE Transmitter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Data Input Rate
          2. 7.2.1.2.2 Interpolation
          3. 7.2.1.2.3 LO Feedthrough and Sideband Correction
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Direct Upconversion (Zero IF) LTE Transmitter
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 Data Input Rate
          2. 7.2.2.2.2 Interpolation
          3. 7.2.2.2.3 LO Feedthrough and Sideband Correction
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
      3. 7.4.3 Assembly
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
        1. 8.1.1.1 Definition of Specifications
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Clarifications for DAC3482 Power Supply and Phase-Locked Loop Specification

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Revision History

Changes from Revision F (August 2015) to Revision G (January 2024)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Changed the Device Information table to the Package Information tableGo
  • Changed JESD204B to LVDS in the Simplified SchematicGo

Changes from Revision E (February 2013) to Revision F (August 2015)

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go
  • Added NFBGA package to DescriptionGo
  • Added additional operation requirement for SLEEP pin if SLEEP pin is set to logic HIGH before and during device power up and initialization - RKD package.Go
  • Added additional circuit configuration for unused terminalsGo
  • Added additional circuit configuration for unused terminalsGo
  • Added additional circuit configuration for unused terminalsGo
  • Added additional circuit configuration for unused terminalsGo
  • Changed DAC3484 to DAC3482 in SDENB descriptionGo
  • Added additional operation requirement for SLEEP pin if SLEEP pin is set to logic HIGH before and during device power up and initialization - ZAY package.Go
  • Changed parameter name Single-Ended Swing Level to Single-Ended Input Level to better reflect the specification for minimum recommended single-ended voltage level.Go
  • Changed parameter name Single-Ended Swing Level to Single-Ended Input Level to better reflect the specification for minimum recommended single-ended voltage level.Go
  • Added DACCLK and OSTR minimum voltage note to Section 5.6 Go
  • Added text and application report link to Section 6.3.3 Go
  • Added reference to LMK0480x family in Section 6.3.3 Go
  • Added pin number per package for LPF pin in Section 6.3.5.2 Go
  • Changed figure and table references in Section 6.3.6 Go
  • Changed first paragraph in Section 6.3.7 Go
  • Deleted redundant text from Section 6.3.11.2 Go
  • Changed point to pointer in Section 6.3.12 Go
  • Added note to Figure 6-32 Go
  • Added VCOM values to Table 6-9 Go
  • Added Section 6.3.15 Go
  • Added clarification on timing requirement acronyms to Section 6.4.1.2. Go
  • Deleted or in Section 6.5.1 descriptionGo
  • Changed P = 3 to P = 4 in Section 6.5.2.2 to reflect the correct example start-up routine configuration Go
  • Added pin description for both packagesGo
  • Changed Config7, bit 3 naming typo Go
  • Changed config10 to config11 and 0x0A to 0x0B in register config11Go
  • Changed QMC offset registers to QMC correction registers in config16 function Go
  • Changed Qfine to fine in config18 function Go
  • Added reference in config26 function Go
  • Added additional operation requirement for SLEEP pin if SLEEP pin is set to logic HIGH before and during device power up and initialization in config27 function Go
  • Changed 1.2VDIG to DIGVDD in config27 functionGo
  • Added pin description for both packages to register config35 descriptionGo
  • Added reference to Digital Input Timing Specifications in register config36 descriptionGo

Changes from Revision D (August 2012) to Revision E (February 2013)

  • Changed Power Supply Specification Table under Electrical Specification. This specification depends on the enhanced production test coverage and is specific to devices with certain date code. Refer to Clarifications for DAC3482 Power Supply and Phase-Locked Loop Specification Section for detailsGo
  • Deleted Note (5) in Power Consumption Specification to reflect the latest DAC3482 speed specification. Go
  • Changed DACCLKP/N typical clock swing specification to reflect commonly used LVPECL driverGo
  • Changed DACCLKP/N typical clock swing specification to reflect commonly used LVPECL driverGo
  • Changed DACCLK driver requirement to reflect actual device performance under commonly used LVPECL driversGo
  • Changed Analog Output Specification Table under Electrical Specification. This specification depends on the enhanced production test coverage and is specific to devices with certain date code. Refer to Clarifications for DAC3482 Power Supply and Phase-Locked Loop Specification Section for detailsGo
  • Added Phase-Locked Loop Specification Table under Electrical Specification. This specification depends on the enhanced production test coverage and is specific to devices with certain date code. Refer to Clarifications for DAC3482 Power Supply and Phase-Locked Loop Specification Section for detailsGo
  • Changed Digital Latency Specification for QMC to reflect the actual DAC3482 parameterGo
  • Changed Digital Latency Specification for Inverse Sinc to reflect the actual DAC3482 parameterGo
  • Changed syncsel_fifoout(3:0) description to clarify the FIFO read pointer reset capture method and limitationGo
  • Changed information to Single Sync Source Mode section to clarify the latency limitation of Single Sync Source ModeGo
  • Added "the effect of bypassing the FIFO" in the Bypass Mode section to clarify the operation of FIFO, LVDS FRAME, and LVDS SYNC in FIFO Bypass ModeGo
  • Changed PLL Mode section with additional operating recommendations for the DAC3482 on-chip PLLGo
  • Changed Data Pattern Checker section with additional operating recommendationsGo
  • Added additional requirements for Block Parity section when byte wide input data mode is selectedGo
  • Changed information to Multi-Device Operation: Single Sync Source Mode section to clarify the latency limitation of Single Sync Source ModeGo
  • Changed Figure 6-42 to clarify the latency limitation of Single Sync Source ModeGo
  • Changed the NCO setting description in the Example Start-up Sequence Section to reflect the example register writesGo
  • Changed pll_vco(6:0) to pll_vco(5:0) to reflect actual bit width in the registerGo
  • Changed config45, bit12:1 default value to reflect the actual default register valueGo
  • Changed config45, bit0 description to clarify additional DAC3482 behaviorGo

Changes from Revision C (June 2012) to Revision D (August 2012)

  • Added thermal information to the Absolute Maximum Ratings tableGo
  • Added Recommended Operating Conditions tableGo
  • Deleted TJ row from top of thermal tableGo
  • Deleted Operating Range section from bottom of Electrical Characteristics – DC Specifications tableGo

Changes from Revision B (September 2011) to Revision C (June 2012)

  • Changed Package options in FeaturesGo
  • Added ZAY packageGo
  • Added ZAY pin functionsGo
  • Added ZAY package to Thermal Information sectionGo
  • Added Input Common Mode max value of 1.6VGo
  • Added information to CLOCK INPUT (DACCLKP/N) in Electrical Characteristics – Digital SpecificationsGo
  • Added information to OUTPUT STROBE (OSTRP/N) in Electrical Characteristics – Digital SpecificationsGo
  • Changed Electrical Characteristics – AC Specifications AC Performance informationGo
  • Changed Figure 5-20 Go
  • Changed Figure 5-21 Go
  • Changed Figure 5-22 Go
  • Changed Figure 5-23 Go
  • Added Figure 5-47 Go
  • Added Figure 5-48 Go
  • Changed config3 to config9 in Section 6.3.3 Go
  • Added information for double-charge-pump current to PLL MODE sectionGo
  • Changed Figure 6-23 Go
  • Changed +3.75 to –3.75 degrees in 1024 steps to +26.5 to –26.5 degrees in 4096 steps in Gain and Phase Correction sectionGo

Changes from Revision A (March 2011) to Revision B (September 2011)

  • Changed ALARM descriptionGo
  • Added notes to Electrical Characteristics – DC SpecificationsGo
  • Deleted TYP and MAX values from VA,B+ Go
  • Changed VCOM MIN value from 1.075V to 1.0VGo
  • Added MIN and MAX values for ZT Go
  • Added fDAC PLL ON MIN of 1000MSPS in Electrical Characteristics – AC SpecificationsGo
  • Added information to Single Sync Source Mode section to clarify the latency limitation of Single Sync Source ModeGo
  • Changed 1.2288GHz to 983.04MHz in PLL Mode descriptionGo
  • Changed data in Table 6-4 Go
  • Deleted 2x in Table 6-6 Go
  • Changed config32 to config 31 in Power-Up Sequence descriptionGo
  • Changed Example Start-up Routine informationGo
  • Changed Table 6-10 Go
  • Changed config5 default value from 0x0000 to NA in Register MapGo
  • Changed register version default value from 0x5409 to 0x540C in Register MapGo
  • Added SIF SYNC to register config32 descriptionGo
  • Changed register config35 descriptionGo
  • Changed register config36 description from 40 ps to 50 psGo
  • Changed register version default value from 0x5409 to 0x540CGo

Changes from Revision * (March 2011) to Revision A (March 2011)

  • Changed from PRODUCT PREVIEW to PRODUCTION DATAGo