SLAS748G March 2011 – January 2024 DAC3482
PRODUCTION DATA
Register Name | Address | Bit | Name | Function | Default Value | |
---|---|---|---|---|---|---|
config0 | 0x00 | 15 | qmc_offset_ena | When set, the digital Quadrature Modulator Correction (QMC) offset correction is enabled. | 0 | |
14 | Reserved | Reserved for factory use. | 0 | |||
13 | qmc_corr_ena | When set, the QMC phase and gain correction circuitry is enabled. | 0 | |||
12 | Reserved | Reserved for factory use. | 0 | |||
11:8 | interp(3:0) | These bits define the interpolation factor | 0100 | |||
interp | Interpolation Factor | |||||
0000 | 1x | |||||
0001 | 2x | |||||
0010 | 4x | |||||
0100 | 8x | |||||
1000 | 16x | |||||
7 | fifo_ena | When set, the FIFO is enabled. When the FIFO is disabled DACCCLKP/N and DATACLKP/N must be aligned (not recommended). | 1 | |||
6 | Reserved | Reserved for factory use. | 0 | |||
5 | Reserved | Reserved for factory use. | 0 | |||
4 | alarm_out_ena | When set, the ALARM pin becomes an output. When cleared, the ALARM pin is 3-stated. | 1 | |||
3 | alarm_out_pol | This bit changes the polarity of the ALARM signal. 0: Negative logic 1: Positive logic | 1 | |||
2 | clkdiv_sync_ena | When set, enables the syncing of the clock divider using the sync source selected by register config32. The internal divided-down clocks will be phase aligned after syncing. See Section 6.5.1 for more details. | 1 | |||
1 | invsinc_ena | When set, the inverse sinc filter is enabled. | 0 | |||
0 | Reserved | Reserved for factory use. | 0 |