SLAS748G March 2011 – January 2024 DAC3482
PRODUCTION DATA
MIN | NOM | MAX | UNIT | |||||
---|---|---|---|---|---|---|---|---|
CLOCK INPUT (DACCLKP/N) | ||||||||
Duty cycle | 40% | 60% | ||||||
DACCLKP/N input frequency | 1250 | MHz | ||||||
OUTPUT STROBE (OSTRP/N) | ||||||||
fOSTR | Frequency | fOSTR = fDACCLK / (n x 8 x Interp) where n is any positive integer, fDACCLK is DACCLK frequency in MHz | fDACCLK / (8 x interp) |
MHz | ||||
Duty cycle | 50% | |||||||
DIGITAL INPUT TIMING SPECIFICATIONS | ||||||||
Timing LVDS inputs: D[15:0]P/N, FRAMEP/N, SYNCP/N, PARITYP/N, double edge latching | ||||||||
ts(DATA) | Setup time, D[15:0]P/N, FRAMEP/N, SYNCP/N and PARITYP/N, valid to either edge of DATACLKP/N | FRAMEP/N reset and frame indicator latched on rising
edge of DATACLKP/N. FRAMEP/N parity bit latched on falling edge of DATACLKP/N. |
Config36 Setting | |||||
datadly | clkdly | |||||||
0 | 0 | 150 | ps | |||||
0 | 1 | 100 | ||||||
0 | 2 | 50 | ||||||
0 | 3 | 0 | ||||||
0 | 4 | -50 | ||||||
0 | 5 | -100 | ||||||
0 | 6 | -150 | ||||||
0 | 7 | -200 | ||||||
1 | 0 | 200 | ||||||
2 | 0 | 250 | ||||||
3 | 0 | 300 | ||||||
4 | 0 | 350 | ||||||
5 | 0 | 400 | ||||||
6 | 0 | 450 | ||||||
7 | 0 | 500 | ||||||
th(DATA) | Hold time, D[15:0]P/N, FRAMEP/N, SYNCP/N and PARITYP/N, valid after either edge of DATACLKP/N | FRAMEP/N reset and frame indicator latched on rising
edge of DATACLKP/N. FRAMEP/N parity bit latched on falling edge of DATACLKP/N. |
Config36 Setting | ps | ||||
datadly | clkdly | |||||||
0 | 0 | 350 | ||||||
0 | 1 | 400 | ||||||
0 | 2 | 450 | ||||||
0 | 3 | 500 | ||||||
0 | 4 | 550 | ||||||
0 | 5 | 600 | ||||||
0 | 6 | 650 | ||||||
0 | 7 | 700 | ||||||
1 | 0 | 300 | ||||||
2 | 0 | 250 | ||||||
3 | 0 | 200 | ||||||
4 | 0 | 150 | ||||||
5 | 0 | 100 | ||||||
6 | 0 | 50 | ||||||
7 | 0 | 0 | ||||||
t(FRAME_SYNC) | FRAMEP/N and SYNCP/N pulse width | fDATACLK is DATACLK frequency in MHz | 1/2fDATACLK | ns | ||||
TIMING OUTPUT STROBE INPUT: DACCLKP/N rising edge LATCHING(1) | ||||||||
ts(OSTR) | Setup time, OSTRP/N valid to rising edge of DACCLKP/N | 0 | ps | |||||
th(OSTR) | Hold time, OSTRP/N valid after rising edge of DACCLKP/N | 300 | ps | |||||
TIMING SYNC INPUT: DACCLKP/N rising edge LATCHING(2) | ||||||||
ts(SYNC_PLL) | Setup time, SYNCP/N valid to rising edge of DACCLKP/N | 200 | ps | |||||
th(SYNC_PLL) | Hold time, SYNCP/N valid after rising edge of DACCLKP/N | 300 | ps | |||||
TIMING SERIAL PORT | ||||||||
ts(SDENB) | Setup time, SDENB to rising edge of SCLK | 20 | ns | |||||
ts(SDIO) | Setup time, SDIO valid to rising edge of SCLK | 10 | ns | |||||
th(SDIO) | Hold time, SDIO valid to rising edge of SCLK | 5 | ns | |||||
t(SCLK) | Period of SCLK | Register config6 read (temperature sensor read) | 1 | µs | ||||
All other registers | 100 | ns | ||||||
td(Data) | Data output delay after falling edge of SCLK | 10 | ns | |||||
tRESET | Minimum RESETB pulse width | 25 | ns |