SLAS748G March   2011  – January 2024 DAC3482

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics – DC Specifications
    6. 5.6  Electrical Characteristics – Digital Specifications
    7. 5.7  Electrical Characteristics – AC Specifications
    8. 5.8  Electrical Characteristics - Phase-Locked Loop Specifications
    9. 5.9  Timing Requirements - Digital Specifications
    10. 5.10 Switching Characteristics – AC Specifications
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Serial Interface
      2. 6.3.2  Data Interface
        1. 6.3.2.1 Word-Wide Format
        2. 6.3.2.2 Byte-Wide Format
      3. 6.3.3  Input FIFO
      4. 6.3.4  FIFO Modes of Operation
        1. 6.3.4.1 Dual Sync Source Mode
        2. 6.3.4.2 Single Sync Source Mode
        3. 6.3.4.3 Bypass Mode
      5. 6.3.5  Clocking Modes
        1. 6.3.5.1 PLL Bypass Mode
        2. 6.3.5.2 PLL Mode
      6. 6.3.6  FIR Filters
      7. 6.3.7  Complex Signal Mixer
        1. 6.3.7.1 Full Complex Mixer
        2. 6.3.7.2 Coarse Complex Mixer
        3. 6.3.7.3 Mixer Gain
        4. 6.3.7.4 Real Channel Upconversion
      8. 6.3.8  Quadrature Modulation Correction (QMC)
        1. 6.3.8.1 Gain and Phase Correction
        2. 6.3.8.2 Offset Correction
        3. 6.3.8.3 Group Delay Correction
      9. 6.3.9  Temperature Sensor
      10. 6.3.10 Data Pattern Checker
      11. 6.3.11 Parity Check Test
        1. 6.3.11.1 Word-by-Word Parity
        2. 6.3.11.2 Block Parity
      12. 6.3.12 DAC3482 Alarm Monitoring
      13. 6.3.13 LVPECL Inputs
      14. 6.3.14 LVDS Inputs
      15. 6.3.15 Unused LVDS Port Termination
      16. 6.3.16 CMOS Digital Inputs
      17. 6.3.17 Reference Operation
      18. 6.3.18 DAC Transfer Function
      19. 6.3.19 Analog Current Outputs
    4. 6.4 Device Functional Modes
      1. 6.4.1 Multi-Device Synchronization
        1. 6.4.1.1 Multi-Device Synchronization: PLL Bypassed with Dual Sync Sources Mode
        2. 6.4.1.2 Multi-Device Synchronization: PLL Enabled with Dual Sync Sources Mode
        3. 6.4.1.3 Multi-Device Operation: Single Sync Source Mode
    5. 6.5 Programming
      1. 6.5.1 Power-Up Sequence
      2. 6.5.2 Example Start-Up Routine
        1. 6.5.2.1 Device Configuration
        2. 6.5.2.2 PLL Configuration
        3. 6.5.2.3 NCO Configuration
        4. 6.5.2.4 Example Start-Up Sequence
    6. 6.6 Register Map
      1. 6.6.1 Register Descriptions
        1. 6.6.1.1  Register Name: config0 – Address: 0x00, Default: 0x049C
        2. 6.6.1.2  Register Name: config1 – Address: 0x01, Default: 0x050E
        3. 6.6.1.3  Register Name: config2 – Address: 0x02, Default: 0x7000
        4. 6.6.1.4  Register Name: config3 – Address: 0x03, Default: 0xF000
        5. 6.6.1.5  Register Name: config4 – Address: 0x04, Default: No RESET Value (WRITE TO CLEAR)
        6. 6.6.1.6  Register Name: config5 – Address: 0x05, Default: Setup and Power-Up Conditions Dependent (WRITE TO CLEAR)
        7. 6.6.1.7  Register Name: config6 – Address: 0x06, Default: No RESET Value (READ ONLY)
        8. 6.6.1.8  Register Name: config7 – Address: 0x07, Default: 0xFFFF
        9. 6.6.1.9  Register Name: config8 – Address: 0x08, Default: 0x0000 (CAUSES AUTO-SYNC)
        10. 6.6.1.10 Register Name: config9 – Address: 0x09, Default: 0x8000
        11. 6.6.1.11 Register Name: config10 – Address: 0x0A, Default: 0x0000
        12. 6.6.1.12 Register Name: config11 – Address: 0x0B, Default: 0x0000
        13. 6.6.1.13 Register Name: config12 – Address: 0x0C, Default: 0x0400
        14. 6.6.1.14 Register Name: config13 – Address: 0x0D, Default: 0x0400
        15. 6.6.1.15 Register Name: config14 – Address: 0x0E, Default: 0x0400
        16. 6.6.1.16 Register Name: config15 – Address: 0x0F, Default: 0x0400
        17. 6.6.1.17 Register Name: config16 – Address: 0x10, Default: 0x0000 (CAUSES AUTO-SYNC)
        18. 6.6.1.18 Register Name: config17 – Address: 0x11, Default: 0x0000
        19. 6.6.1.19 Register Name: config18 – Address: 0x12, Default: 0x0000 (CAUSES AUTO-SYNC)
        20. 6.6.1.20 Register Name: config19 – Address: 0x13, Default: 0x0000
        21. 6.6.1.21 Register Name: config20 – Address: 0x14, Default: 0x0000
        22. 6.6.1.22 Register Name: config21 – Address: 0x15, Default: 0x0000
        23. 6.6.1.23 Register name: config22 – Address: 0x16, Default: 0x0000
        24. 6.6.1.24 Register Name: config23 – Address: 0x17, Default: 0x0000
        25. 6.6.1.25 Register Name: config24 – Address: 0x18, Default: NA
        26. 6.6.1.26 Register Name: config25 – Address: 0x19, Default: 0x0440
        27. 6.6.1.27 Register Name: config26 – Address: 0x1A, Default: 0x0020
        28. 6.6.1.28 Register Name: config27 – Address: 0x1B, Default: 0x0000
        29. 6.6.1.29 Register Name: config28 – Address: 0x1C, Default: 0x0000
        30. 6.6.1.30 Register Name: config29 – Address: 0x1D, Default: 0x0000
        31. 6.6.1.31 Register Name: config30 – Address: 0x1E, Default: 0x1111
        32. 6.6.1.32 Register Name: config31 – Address: 0x1F, Default: 0x1140
        33. 6.6.1.33 Register Name: config32 – Address: 0x20, Default: 0x2400
        34. 6.6.1.34 Register Name: config33 – Address: 0x21, Default: 0x0000
        35. 6.6.1.35 Register Name: config34 – Address: 0x22, Default: 0x1B1B
        36. 6.6.1.36 Register Name: config35 – Address: 0x23, Default: 0xFFFF
        37. 6.6.1.37 Register Name: config36 – Address: 0x24, Default: 0x0000
        38. 6.6.1.38 Register Name: config37 – Address: 0x25, Default: 0x7A7A
        39. 6.6.1.39 Register Name: config38 – Address: 0x26, Default: 0xB6B6
        40. 6.6.1.40 Register Name: config39 – Address: 0x27, Default: 0xEAEA
        41. 6.6.1.41 Register Name: config40 – Address: 0x28, Default: 0x4545
        42. 6.6.1.42 Register Name: config41 – Address: 0x29, Default: 0x1A1A
        43. 6.6.1.43 Register Name: config42 – Address: 0x2A, Default: 0x1616
        44. 6.6.1.44 Register Name: config43 – Address: 0x2B, Default: 0xAAAA
        45. 6.6.1.45 Register Name: config44 – Address: 0x2C, Default: 0xC6C6
        46. 6.6.1.46 Register Name: config45 – Address: 0x2D, Default: 0x0004
        47. 6.6.1.47 Register Name: config46 – Address: 0x2E, Default: 0x0000
        48. 6.6.1.48 Register Name: config47 – Address: 0x2F, Default: 0x0000
        49. 6.6.1.49 Register Name: config48 – Address: 0x30, Default: 0x0000
        50. 6.6.1.50 Register Name: version– Address: 0x7F, Default: 0x540C (READ ONLY)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 IF Based LTE Transmitter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Data Input Rate
          2. 7.2.1.2.2 Interpolation
          3. 7.2.1.2.3 LO Feedthrough and Sideband Correction
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Direct Upconversion (Zero IF) LTE Transmitter
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 Data Input Rate
          2. 7.2.2.2.2 Interpolation
          3. 7.2.2.2.3 LO Feedthrough and Sideband Correction
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
      3. 7.4.3 Assembly
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
        1. 8.1.1.1 Definition of Specifications
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Clarifications for DAC3482 Power Supply and Phase-Locked Loop Specification

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

GUID-71E086D1-BA98-43B6-8D37-38F4D17897CC-low.gifFigure 4-1 RKD Package, 88-Pin WQFN-MR with Exposed Thermal Pad (Top View)
Table 4-1 RKD Package Pin Functions
PINI/ODESCRIPTION
NAMENO.
AVDDA36, A37, A38, A40, A41, A42, B31IAnalog supply voltage (3.3V)
ALARMB29OCMOS output for ALARM condition. The ALARM output functionality is defined through the config7 register. Default polarity is active high, but can be changed to active low via config0 alarm_out_pol control bit.
BIASJA33OFull-scale output current bias. For 30-mA full-scale output current, connect 1.28kΩ to ground. Change the full-scale output current through coarse_dac(3:0) in config3, bit<15:12>.
CLKVDDA4IInternal clock buffer supply voltage. (1.2 V)
It is recommended to isolate this supply from DIGVDD and DACVDD.
D[15..0]PA7, A8, B9, B10, A12, A13, A14, A15, B17, B18, B19, B20, A23, A24, B23, B24ILVDS positive input data bits 0 through 15. Internal 100Ω termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR) and can be transferred in either byte-wide or word-wide mode. In byte-wide mode the unused pins can be left unconnected.
D15P is most significant data bit (MSB) in word-wide mode
D7P is most significant data bit (MSB) in byte-wide mode
D0P is least significant data bit (LSB)
The order of the bus can be reversed via config2 revbus bit.
D[15..0]NB7, B8, A10, A11, B11, B12, B13, B14, A19, A20, A21, A22, B21, B22, A26, A27ILVDS negative input data bits 0 through 15. (See D[15:0]P description above.)
DACCLKPA3IPositive external LVPECL clock input for DAC core with a self-bias.
DACCLKNB3IComplementary external LVPECL clock input for DAC core. (see the DACCLKP description above.)
DACVDDA35, A39, A43IDAC core supply voltage. (1.2V). It is recommended to isolate this supply from CLKVDD and DIGVDD.
DATACLKPA16ILVDS positive input data clock. Internal 100-Ω termination resistor. Input data D[15:0]P/N is latched on both edges of DATACLKP/N (Double Data Rate).
DATACLKNB15ILVDS negative input data clock. (See DATACLKP description above.)
DIGVDDA6, A9, A25, A28IDigital supply voltage. (1.2V). It is recommended to isolate this supply from CLKVDD and DACVDD.
EXTIOA34I/OUsed as external reference input when internal reference is disabled through config27 extref_ena = 1b. Used as internal reference output when config27 extref_ena = 0b (default). Requires a 0.1μF decoupling capacitor to AGND when used as reference output.
FRAMEPB16ILVDS frame indicator positive input. Internal 100-Ω termination resistor. The main functions of this input are to reset the FIFO or to be used as a syncing source. These two functions are captured with the rising edge of DATACLKP/N. The signal captured by the falling edge of DATACLKP/N can be used as a block parity bit. The FRAMEP/N signal should be edge-aligned with D[15:0]P/N.
FRAMENA18ILVDS frame indicator negative input. (See the FRAMEP description above.)
GNDC1, C2, C3, C4, B32, B33, B38, B39, Thermal PadIThese pins are ground for all supplies.
IOUTIPB36OI-Channel DAC current output. Connect directly to ground if unused.
IOUTINB37OI-Channel DAC complementary current output. Connect directly to ground if unused.
IOUTQPB35OQ-Channel DAC current output. Connect directly to ground if unused.
IOUTQNB34OQ-Channel DAC complementary current output. Connect directly to ground if unused.
IOVDDB6, A17, B25ISupply voltage for all digital I/O. (3.3V)
LPFA1I/OPLL loop filter connection. If not using the clock multiplying PLL, the LPF pin can be left unconnected.
OSTRPA2ILVPECL output strobe positive input. This positive/negative pair is captured with the rising edge of DACCLKP/N. It is used to sync the divided-down clocks and FIFO output pointer in Dual Sync Sources Mode. If unused it can be left unconnected.
OSTRNB2ILVPECL output strobe negative input. (See the OSTRP description)
PARITYPB26IOptional LVDS positive input parity bit. The PARITYP/N LVDS pair has an internal 100Ω termination resistor. If unused it can be left unconnected.
PARITYNA29IOptional LVDS negative input parity bit.
PLLAVDDB1IPLL analog supply voltage. (3.3V)
SCLKA31ISerial interface clock. Internal pull-down.
SDENBB28IActive low serial data enable, always an input to the DAC3482. Internal pull-up.
SDIOA30I/OSerial interface data. Bi-directional in 3-pin mode (default) and uni-directional in 4-pin mode. Internal pull-down.
SDOB27OUni-directional serial interface data in 4-pin mode. The SDO pin is tri-stated in 3-pin interface mode (default).
SLEEPB40IActive high asynchronous hardware power-down input. Internal pull-down. If SLEEP pin is set to logic HIGH before and during device power-up and initialization, the fuse_sleep bit in register 0x1B, bit 11 must be written after register 0x23 during device initialization register setup.
SYNCPA5IOptional LVDS SYNC positive input. The SYNCP/N LVDS pair has an internal 100Ω termination resistor. If unused it can be left unconnected.
SYNCNB5IOptional LVDS SYNC negative input.
RESETBB30IActive low input for chip RESET, which resets all the programming registers to their default state. Internal pull-up.
TXENABLEA32ITransmit enable active high input. Internal pull-down.
To enable analog output data transmission, set sif_txenable in register config3 to 1b or pull CMOS TXENABLE pin to high.
To disable analog output, set sif_txenable to 0b and pull CMOS TXENABLE pin to low. The digital logic section is forced to all 0, and any input data is ignored.
TESTMODEA44IThis pin is used for factory testing. Internal pull-down. Leave unconnected for normal operation.
VFUSEB4IDigital supply voltage. This supply pin is also used for factory fuse programming. Connect to DACVDD for normal operation.
GUID-A9050144-00FA-4CE1-A49C-16DD2EAB31C6-low.gifFigure 4-2 ZAY Package, 196-Ball NFBGA (Top View)
Table 4-2 ZAY Package Pin Functions
PINI/ODESCRIPTION
NAMENO.
AVDDD10, E11, F11, G11, H11, J11, K11, L10IAnalog supply voltage (3.3V)
ALARMN12OCMOS output for ALARM condition. The ALARM output functionality is defined through the config7 register. Default polarity is active low, but can be changed to active high via config0 alarm_out_pol control bit.
BIASJH12OFull-scale output current bias. For 30mA full-scale output current, connect 1.28kΩ to ground. Change the full-scale output current through coarse_dac(3:0) in config3, bit<15:12>.
CLKVDDC12IInternal clock buffer supply voltage. (1.2V)
It is recommended to isolate this supply from DIGVDD and DACVDD.
D[15..0]PN4, N3, N2, N1, M2, L2, K2, J2, F2, E2, D2, C2, A1, A2, A3, A4ILVDS positive input data bits 0 through 15. Internal 100Ω termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR).
D15P is most significant data bit (MSB)
D0P is least significant data bit (LSB)
The order of the bus can be reversed via config2 revbus bit.
D[15..0]NP4, P3, P2, P1, M1, L1, K1, J1, F1, E1, D1, C1, B1, B2, B3, B4ILVDS negative input data bits 0 through 15. (See D[15:0]P description above.)
DACCLKPA12IPositive external LVPECL clock input for DAC core with a self-bias.
DACCLKNA11IComplementary external LVPECL clock input for DAC core. (see the DACCLKP description above.)
DACVDDD9, E9, E10, F10, G10, H10, J10, K9, K10, L9IDAC core supply voltage. (1.2V). It is recommended to isolate this supply from CLKVDD and DIGVDD.
DATACLKPG2ILVDS positive input data clock. Internal 100Ω termination resistor. Input data D[15:0]P/N is latched on both edges of DATACLKP/N (Double Data Rate).
DATACLKNG1ILVDS negative input data clock. (See DATACLKP description above.)
DIGVDDE5, E6, E7, F5, J5, K5, K6, K7IDigital supply voltage. (1.2V). It is recommended to isolate this supply from CLKVDD and DACVDD.
EXTIOG12I/OUsed as external reference input when internal reference is disabled through config27 extref_ena = 1b. Used as internal reference output when config27 extref_ena = 0b (default). Requires a 0.1-μF decoupling capacitor to AGND when used as reference output.
FRAMEPH2ILVDS frame indicator positive input. Internal 100-Ω termination resistor.
The main functions of this input are to reset the FIFO pointer or to be used as a syncing source. These two functions are captured with the rising edge of DATACLKP/N. The signal captured by the falling edge of DATACLKP/N can be used as a block parity bit. The FRAMEP/N signal should be edge-aligned with D[15:0]P/N.
Additionally it is used to indicate the beginning of the frame.
FRAMENH1ILVDS frame indicator negative input. (See the FRAMEP description above.)
GNDA10, A13, A14, B10, B11, B12, B13, B14, C5, C6, C7, C8, C9, C10, C13, C14, D8, D13, D14, E8, E12, E13, F6, F7, F8, F9, F12, F13, G6, G7, G8, G9, G13, G14, H6, H7, H8, H9, H13, H14, J6, J7, J8, J9, J12, J13, K8, K13, L8, L13, L14, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, N13, N14, P13, P14IThese pins are ground for all supplies.
IOUTIPF14OI-Channel DAC current output. Connect directly to ground if unused.
IOUTINE14OI-Channel DAC complementary current output. Connect directly to ground if unused.
IOUTQPJ14OQ-Channel DAC current output. Connect directly to ground if unused.
IOUTQNK14OQ-Channel DAC complementary current output. Connect directly to ground if unused.
IOVDDD5, D6, G5, H5, L5, L6ISupply voltage for all digital I/O. (3.3V)
LPFD12IPLL loop filter connection. If not using the clock multiplying PLL, the LPF pin can be left unconnected.
OSTRPA9ILVPECL output strobe positive input. This positive/negative pair is captured with the rising edge of DACCLKP/N. It is used for multiple DAC synchronization. If unused it can be left unconnected.
OSTRNB9ILVPECL output strobe negative input. (See the OSTRP description above.)
PARITYPN5IOptional LVDS positive input parity bit. The PARITYP/N LVDS pair has an internal 100-Ω termination resistor. If unused it can be left unconnected.
PARITYNP5IOptional LVDS negative input parity bit.
PLLAVDDC11, D11IPLL analog supply voltage. (3.3V)
SCLKP9ISerial interface clock. Internal pull-down.
SDENBP10IActive low serial data enable, always an input to the DAC3482. Internal pull-up.
SDIOP11I/OSerial interface data. Bi-directional in 3-pin mode (default) and 4-pin mode. Internal pull-down.
SDOP12OUni-directional serial interface data in 4-pin mode. The SDO pin is three-stated in 3-pin interface mode (default).
SLEEPB8IActive high asynchronous hardware power-down input. Internal pull-down. If SLEEP pin is set to logic HIGH before and during device power-up and initialization, the fuse_sleep bit in register 0x1B, bit 11 must be written after register 0x23 during device initialization register setup.
SYNCPA5IOptional LVDS SYNC positive input. The SYNCP/N LVDS pair has an internal 100-Ω termination resistor. If unused it can be left unconnected.
SYNCNB5ILVDS SYNC negative input.
RESETBN10IActive low input for chip RESET, which resets all the programming registers to their default state. Internal pull-up.
TXENABLEN9ITransmit enable active high input. Internal pull-down.
To enable analog output data transmission, set sif_txenable in register config3 to 1b or pull CMOS TXENABLE pin to high.
To disable analog output, set sif_txenable to 0b and pull CMOS TXENABLE pin to low. The DAC output is forced to midscale.
TESTMODEA8OThis pin is used for factory testing. Internal pull-down. Leave unconnected for normal operation.
VFUSED7IDigital supply voltage. This supply pin is also used for factory fuse programming. Connect to DACVDD for normal operation.