SLAS748G March 2011 – January 2024 DAC3482
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Resolution | 16 | Bits | ||||
DC ACCURACY | ||||||
DNL | Differential nonlinearity | 1 LSB = IOUTFS/216 | ±2 | LSB | ||
INL | Integral nonlinearity | ±4 | LSB | |||
ANALOG OUTPUT | ||||||
Coarse gain linearity | ±0.04 | LSB | ||||
Offset error | Mid code offset | ±0.001 | %FSR | |||
Gain error | With external reference | ±2 | %FSR | |||
With internal reference | ±2 | %FSR | ||||
Gain mismatch | With internal reference | ±2 | %FSR | |||
Full scale output current | 10 | 20 | 30 | mA | ||
Output compliance range | –0.5 | 0.6 | V | |||
Output resistance | 300 | kΩ | ||||
Output capacitance | 5 | pF | ||||
REFERENCE OUTPUT | ||||||
VREF | Reference output voltage | 1.2 | V | |||
Reference output current(2) | 100 | nA | ||||
REFERENCE INPUT | ||||||
VEXTIO | Input voltage range | External Reference Mode | 0.6 | 1.2 | 1.25 | V |
Input resistance | 1 | MΩ | ||||
Small signal bandwidth | 472 | kHz | ||||
Input capacitance | 100 | pF | ||||
TEMPERATURE COEFFICIENTS | ||||||
Offset drift | ±1 | ppm/°C | ||||
Gain drift | With external reference | ±15 | ppm/°C | |||
With internal reference | ±30 | ppm/°C | ||||
Reference voltage drift | ±8 | ppm/°C | ||||
POWER SUPPLY(4) | ||||||
AVDD, IOVDD, PLLAVDD | All conditions | 3.14 | 3.3 | 3.46 | V | |
DIGVDD | All conditions | 1.14 | 1.2 | 1.32 | V | |
CLKVDD, DACVDD(5) | FDAC Sample Rate ≤ 1.25GSPS, PLL OFF | 1.14 | 1.2 | 1.32 | V | |
FDAC Sample Rate ≤ 1GSPS, PLL ON | 1.14 | 1.2 | 1.32 | |||
FDAC Sample Rate ≥ 1GSPS, PLL ON | 1.25 | 1.29 | 1.32 | |||
PSRR | Power supply rejection ratio | DC tested | ±0.2 | %FSR/V | ||
POWER CONSUMPTION | ||||||
I(AVDD) | Analog supply current(3) | MODE 1 fDAC = 1.25GSPS, 2x interpolation, Mixer on, QMC on, invsinc on, PLL enabled, 20mA FS output, IF = 200MHz | 80 | 85 | mA | |
I(DIGVDD) | Digital supply current | 390 | 450 | mA | ||
I(DACVDD) | DAC supply current | 30 | 50 | mA | ||
I(CLKVDD) | Clock supply current | 95 | 110 | mA | ||
P | Power dissipation | 882 | 980 | mW | ||
I(AVDD) | Analog supply current(3) | MODE 2 fDAC = 1.25GSPS, 2x interpolation, Mixer on, QMC on, invsinc on, PLL disabled, 20mA FS output, IF = 200MHz | 65 | mA | ||
I(DIGVDD) | Digital supply current | 385 | mA | |||
I(DACVDD) | DAC supply current | 30 | mA | |||
I(CLKVDD) | Clock supply current | 70 | mA | |||
P | Power dissipation | 800 | mW | |||
I(AVDD) | Analog supply current(3) | MODE 3 fDAC = 625MSPS, 2x interpolation, Mixer on, QMC on, invsinc off, PLL disabled, 20mA FS output, IF = 200MHz | 65 | mA | ||
I(DIGVDD) | Digital supply current | 190 | mA | |||
I(DACVDD) | DAC supply current | 15 | mA | |||
I(CLKVDD) | Clock supply current | 45 | mA | |||
P | Power dissipation | 515 | mW | |||
I(AVDD) | Analog supply current(3) | MODE 4 fDAC = 1.25GSPS, 2x interpolation, Mixer on, QMC on, invsinc on, PLL enabled, I/Q output sleep, IF = 200MHz, | 35 | mA | ||
I(DIGVDD) | Digital supply current | 395 | mA | |||
I(DACVDD) | DAC supply current | 30 | mA | |||
I(CLKVDD) | Clock supply current | 95 | mA | |||
P | Power dissipation | 740 | mW | |||
I(AVDD) | Analog supply current(3) | Mode 5 Power-Down mode: No clock, DAC on sleep mode (clock receiver sleep), I/Q output sleep, static data pattern | 20 | mA | ||
I(DIGVDD) | Digital supply current | 10 | mA | |||
I(DACVDD) | DAC supply current | 4 | mA | |||
I(CLKVDD) | Clock supply current | 10 | mA | |||
P | Power dissipation | 95 | mW | |||
I(AVDD) | Analog supply current(4) | Mode 6 fDAC = 1GSPS, 2x interpolation, Mixer off, QMC off, invsinc off, PLL enabled, 20mA FS output, IF = 200MHz | 80 | mA | ||
I(DIGVDD) | Digital supply current | 200 | mA | |||
I(DACVDD) | DAC supply current | 25 | mA | |||
I(CLKVDD) | Clock supply current | 85 | mA | |||
P | Power dissipation | 636 | mW |