SLAS808E February   2012  – September 2015 DAC34SH84

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - Digital Specifications
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Timing Requirements - Digital Specifications
    9. 6.9  Switching Characteristics - AC Specifications
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Serial Interface
      2. 7.3.2  Data Interface
      3. 7.3.3  Data Format
      4. 7.3.4  Input FIFO
      5. 7.3.5  FIFO Modes of Operation
        1. 7.3.5.1 Dual-Sync-Sources Mode
        2. 7.3.5.2 Single-Sync-Source Mode
        3. 7.3.5.3 Bypass Mode
      6. 7.3.6  Clocking Modes
        1. 7.3.6.1 PLL Bypass Mode
        2. 7.3.6.2 PLL Mode
      7. 7.3.7  FIR Filters
      8. 7.3.8  Complex Signal Mixer
        1. 7.3.8.1 Full Complex Mixer
        2. 7.3.8.2 Coarse Complex Mixer
        3. 7.3.8.3 Mixer Gain
        4. 7.3.8.4 Real Channel Upconversion
      9. 7.3.9  Quadrature Modulation Correction (QMC)
        1. 7.3.9.1 Gain and Phase Correction
        2. 7.3.9.2 Offset Correction
      10. 7.3.10 Temperature Sensor
      11. 7.3.11 Data Pattern Checker
      12. 7.3.12 Parity Check Test
        1. 7.3.12.1 32-Bit Parity
        2. 7.3.12.2 Dual 16-Bit Parity
      13. 7.3.13 DAC34SH84 Alarm Monitoring
      14. 7.3.14 LVPECL Inputs
      15. 7.3.15 LVDS Inputs
      16. 7.3.16 CMOS Digital Inputs
      17. 7.3.17 Reference Operation
      18. 7.3.18 DAC Transfer Function
      19. 7.3.19 Analog Current Outputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Multi-Device Synchronization
        1. 7.4.1.1 Multi-Device Synchronization: PLL Bypassed with Dual Sync Sources Mode
        2. 7.4.1.2 Multi-Device Synchronization: PLL Enabled with Dual Sync Sources Mode
        3. 7.4.1.3 Multi-Device Operation: Single Sync Source Mode
    5. 7.5 Programming
      1. 7.5.1 Power-Up Sequence
      2. 7.5.2 Example Start-Up Routine
        1. 7.5.2.1 Device Configuration
        2. 7.5.2.2 PLL Configuration
        3. 7.5.2.3 NCO Configuration
        4. 7.5.2.4 Example Start-Up Sequence
    6. 7.6 Register Map
      1. 7.6.1 Register Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 IF Based LTE Transmitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Data Input Rate
          2. 8.2.1.2.2 Interpolation
          3. 8.2.1.2.3 LO Feedthrough and Sideband Correction
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Direct Upconversion (Zero IF) LTE Transmitter
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Data Input Rate
          2. 8.2.2.2.2 Interpolation
          3. 8.2.2.2.3 LO Feedthrough and Sideband Correction
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Assembly
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Definition of Specifications
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Low Power: 1.8 W at 1.5 GSPS, Full Operating Condition
  • Multi-DAC Synchronization
  • Selectable 2×, 4×, 8×, 16× Interpolation Filter
    • Stop-Band Attenuation > 90 dBc
  • Flexible On-Chip Complex Mixing
    • Two Independent Fine Mixers With 32-Bit NCOs
    • Power-Saving Coarse Mixers: ±n × fS / 8
  • High-Performance, Low-Jitter Clock-Multiplying PLL
  • Digital I and Q Correction
    • Gain, Phase and Offset
  • Digital Inverse Sinc Filters
  • 32-Bit DDR Flexible LVDS Input Data Bus
    • 8-Sample Input FIFO
    • Supports Data Rates up to 750 MSPS
    • Data Pattern Checker
    • Parity Check
  • Temperature Sensor
  • Differential Scalable Output: 10 mA to 30 mA
  • 196-Ball, 12-mm × 12-mm NFBGA

2 Applications

  • Cellular Base Stations
  • Diversity Transmit
  • Wideband Communications

3 Description

The DAC34SH84 is a very low-power, high-dynamic range, quad-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.5 GSPS.

The device includes features that simplify the design of complex transmit architectures: 2× to 16× digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. Independent complex mixers allow flexible carrier placement.

A high-performance low-jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital quadrature modulator correction (QMC) enables complete IQ compensation for gain, offset and phase between channels in direct upconversion applications.

Digital data is input to the device through a 32-bit wide LVDS data bus with on-chip termination. The wide bus allows the processing of high-bandwidth signals. The device includes a FIFO, data pattern checker, and parity test to ease the input interface. The interface also allows full synchronization of multiple devices.

The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a 196-ball, 12-mm × 12-mm, 0.8-mm pitch NFBGA package.

The DAC34SH84 low-power, high-bandwidth support, superior crosstalk, high dynamic range, and features are an ideal fit for next-generation communication systems.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DAC34SH84 NFBGA (196) 12.00 mm x 12.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

DAC34SH84 fp_schem_las808.gif

4 Revision History

Changes from D Revision (October 2012) to E Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go

Changes from C Revision (October 2012) to D Revision

  • Changed from ADVANCE INFORMATION to PRODUCTION DATAGo

Changes from B Revision (July 2012) to C Revision

  • Added Phase-Locked Loop section to Electrical Characteristics — Digital tableGo
  • Revised the text in the Bypass Mode sectionGo
  • Added reference to new PLL section in Electrical Characteristics – Digital tableGo
  • Added a sentence to the last paragraph in the Data Pattern Checker sectionGo
  • Changed version registerGo
  • Changed contents of version registerGo

Changes from A Revision (June 2012) to B Revision

  • Added thermal information to the Absolute Maximum Ratings tableGo
  • Added Recommended Operating Conditions tableGo
  • Deleted OPERATING RANGE section from bottom of Electrical Characteristics - DC Specifications tableGo
  • Changed DAC Wake-up Time in Electrical Characteristics – AC SpecificationsGo