SLASEA3D December 2016 – December 2023 DAC38RF80 , DAC38RF83 , DAC38RF84 , DAC38RF85 , DAC38RF90 , DAC38RF93
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | x |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | ENDIVCLK | R/W | 1 | Enable divided by 5 output clock |
14:3 | CLKBYP | R/W | 00 | Serdes clock bypass |
12:11 | LB | R/W | 00 | Serdes PLL loop bandwidth |
10 | SLEEPPLL | R/W | 0 | Serdes PLL Sleep |
9 | VRANGE | R/W | 1 | Serdes PLL loop filter range |
8:1 | MPY | R/W | 00010100 | Serdes reference clock multiplication factor Table 7-4 |
0 | CORRECT | R/W | 0 | AND'ed with LANE_ENA so it must be set to 1 for correct behavior |