SLASEA3D December 2016 – December 2023 DAC38RF80 , DAC38RF83 , DAC38RF84 , DAC38RF85 , DAC38RF90 , DAC38RF93
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | x |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | DUAL_IQ | R/W | 0 | When asserted the SLICE uses both IQ paths |
14 | ISFIR_ENA | R/W | 0 | Turns on the inverse sync filter for the AB and CD paths when programmed to 1. |
13 | Not used | R/W | 0 | Not used |
12:8 | INTERP | R/W | 00010 | Determines the interpolation amount. 00000: 1x 00001: 2x 00010: 4x 00011: 6x 00100: 8x 00101: 10x 00110: 12x 01000: 16x 01001: 18x 01010: 20x 01100: 24x |
7 | ALM_ZEROS_TXEN | R/W | 1 | When asserted any alarm that isn’t masked will mid-level the DAC output by setting the txenable_from_dig to ‘0’ |
6 | DAC_COMPLEMENT | R/W | 0 | When asserted the DAC output will be 2's complemented. This helps with hookup at the board level. |
5 | ALM_ZEROS_JESD | R/W | 1 | When asserted any alarm that isn’t masked will zero the data coming out of the JESD block. |
4 | ALM_OUT_ENA | R/W | 1 | When asserted the output from the selected SLICE will be passed on to the MASTER alarm control if it is also turned on then the alarm will be sent to the pad_alarm pin. |
3 | PAPA_ENA | R/W | 0 | Turns on the Power Amp Protection logic for path A. |
2 | PAPB_ENA | R/W | 0 | Turns on the Power Amp Protection logic for path B. |
1 | PAPC_ENA | R/W | 0 | Turns on the Power Amp Protection logic for path C. |
0 | PAPD_ENA | R/W | 0 | Turns on the Power Amp Protection logic for path D. |