SLASEA6D
February 2017 – June 2020
DAC38RF82
,
DAC38RF89
PRODUCTION DATA.
1
Features
2
Applications
3
Description
32x6 MHz 256-QAM Carriers
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics - DC Specifications
7.6
Electrical Characteristics - Digital Specifications
7.7
Electrical Characteristics - AC Specifications
7.8
PLL/VCO Electrical Characteristics
7.9
Timing Requirements
7.10
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagrams
8.3
Feature Description
8.3.1
SerDes Inputs
8.3.2
SerDes Rate
8.3.3
SerDes PLL
8.3.4
SerDes Equalizer
8.3.5
JESD204B Descrambler
8.3.6
JESD204B Frame Assembly
8.3.7
SYNC Interface
8.3.8
Single or Dual Link Configuration
8.3.9
Multi-Device Synchronization
8.3.10
SYSREF Capture Circuit
8.3.11
SerDes Test Modes through Serial Programming
8.3.12
SerDes Test Modes through IEEE 1500 Programming
8.3.13
Error Counter
8.3.14
Eye Scan
8.3.15
JESD204B Pattern Test
8.3.16
Wideband DUC (wide-DUC)
8.3.17
Interpolation Block
8.3.17.1
Multi-DUC input
8.3.17.2
Interpolation Filters
8.3.17.3
JESD204B Modes, Interpolation and Clock phase Programming
8.3.17.4
Digital Quadrature Modulator
8.3.17.5
Low Power Coarse Resolution Mixing Modes
8.3.17.6
Inverse Sinc Filter
8.3.18
PA Protection Block
8.3.19
Gain Block
8.3.20
Output Summation
8.3.21
Output Delay
8.3.22
Polarity Inversion
8.3.23
Temperature Sensor
8.3.24
Alarm Monitoring
8.3.25
Differential Clock Inputs
8.3.26
CMOS Digital Inputs
8.3.27
DAC Fullscale Output Current
8.3.28
Current Steering DAC Architecture
8.3.29
DAC Transfer Function
8.4
Device Functional Modes
8.4.1
Clocking Modes
8.4.2
PLL Bypass Mode Programming
8.4.3
Internal PLL/VCO
8.4.4
CLKOUT
8.4.5
Serial Peripheral Interface (SPI)
8.4.5.1
NORMAL (RW)
8.4.5.2
WRITE_TO_CLEAR (W0C)
8.4.5.3
Writing to Reserved Bits
8.5
Register Maps
8.5.1
Chip Reset and Configuration Register (address = 0x00) [reset = 0x5803]
Table 48.
RESET_CONFIG Field Descriptions
8.5.2
IO Configuration Register (address = 0x01) [reset = 0x1800]
Table 49.
IO_CONFIG Field Descriptions
8.5.3
Lane Single Detect Alarm Mask Register (address = 0x02) [reset = 0xFFFF]
Table 50.
ALM_SD_MASK Field Descriptions
8.5.4
Clock Alarms Mask Register (address = 0x03) [reset = 0xFFFF
Table 51.
ALM_CLK_MASK Field Descriptions
8.5.5
SERDES Loss of Signal Detection Alarms Register (address = 0x04) [reset = variable]
Table 52.
ALM_SD_DET Field Descriptions
8.5.6
SYSREF Alignment Circuit Alarms Register (address = 0x05) [reset = variable]
Table 53.
ALM_SYSREF_DET Field Descriptions
8.5.7
Temperature Sensor and PLL Loop Voltage Register (address = 0x06) [reset = variable]
Table 54.
TEMP_PLLVOLT Field Descriptions
8.5.8
Page Set Register (address = 0x09) [reset = 0x0000]
Table 55.
PAGE_SET Field Descriptions
8.5.9
SYSREF Align to r1 and r3 Count Register (address = 0x78) [reset = 0x0000]
Table 56.
SYSREF_ALIGN_R Field Descriptions
8.5.10
SYSREF Phase Count 1 and 2 Register (address = 0x79) [reset = 0x0000]
Table 57.
SYSREF12_CNT Field Descriptions
8.5.11
SYSREF Phase Count 3 and 4 Register (address = 0x7A) [reset = 0x0000]
Table 58.
SYSREF34_CNT Field Descriptions
8.5.12
Vendor ID and Chip Version Register (address = 0x7F) [reset = 0x0009]
Table 59.
VENDOR_VER Field Descriptions
8.5.13
Multi-DUC Configuration (PAP, Interpolation) Register (address = 0x0A) [reset = 0x02B0]
Table 60.
MULTIDUC_CFG1 Field Descriptions
8.5.14
Multi-DUC Configuration (Mixers) Register (address = 0x0C) [reset = 0x2402]
Table 61.
MULTIDUC_CFG2 Field Descriptions
8.5.15
JESD FIFO Control Register (address = 0x0D)[reset = 0x8000]
Table 62.
JESD_FIFO Field Descriptions
8.5.16
Alarm Mask 1 Register (address = 0x0E) [reset = 0x00FF]
Table 63.
ALM_MASK1 Field Descriptions
8.5.17
Alarm Mask 2 Register (address = 0x0F) [reset = 0xFFFF]
Table 64.
ALM_MASK2 Field Descriptions
8.5.18
Alarm Mask 3 Register (address = 0x10) [reset = 0xFFFF]
Table 65.
ALM_MASK3 Field Descriptions
8.5.19
Alarm Mask 4 Register (address = 0x11) [reset = 0xFFFF]
Table 66.
ALM_MASK4 Field Descriptions
8.5.20
JESD Lane Skew Register (address = 0x12) [reset = 0x0000]
Table 67.
JESD_LN_SKEW Field Descriptions
8.5.21
CMIX Configuration Register (address = 0x17) [reset = 0x0000]
Table 68.
CMIX Field Descriptions
8.5.22
Output Summation and Delay Register (address = 0x19) [reset = 0x0000]
Table 69.
OUTSUM Field Descriptions
8.5.23
NCO Phase Path AB Register (address = 0x1C) [reset = 0x0000]
Table 70.
PHASE_NCOAB Field Descriptions
8.5.24
NCO Phase Path CD Register (address = 0x1D) [reset = 0x0000]
Table 71.
PHASE_NCOCD Field Descriptions
8.5.25
NCO Frequency Path AB Register (address = 0x1E-0x20) [reset = 0x0000 0000 0000]
Table 72.
FREQ_NCOAB Field Descriptions
8.5.26
NCO Frequency Path CD Register (address = 0x21-0x23) [reset = 0x0000 0000 0000]
Table 73.
FREQ_NCOCD Field Descriptions
8.5.27
SYSREF Use for Clock Divider Register (address = 0x24) [reset = 0x0010]
Table 74.
SYSREF_CLKDIV Field Descriptions
8.5.28
Serdes Clock Control Register (address = 0x25) [reset = 0x7700]
Table 75.
SERDES_CLK Field Descriptions
8.5.29
Sync Source Control 1 Register (address = 0x27) [reset = 0x1144]
Table 76.
SYNCSEL1 Field Descriptions
8.5.30
Sync Source Control 2 Register (address = 0x28) [reset = 0x0000]
Table 77.
SYNCSEL2 Field Descriptions
8.5.31
PAP path AB Gain Attenuation Step Register (address = 0x29) [reset = 0x0000]
Table 78.
PAP_GAIN_AB Field Descriptions
8.5.32
PAP path AB Wait Time Register (address = 0x2A) [reset = 0x0000]
Table 79.
PAP_WAIT_AB Field Descriptions
8.5.33
PAP path CD Gain Attenuation Step Register (address = 0x2B) [reset = 0x0000]
Table 80.
PAP_GAIN_CD Field Descriptions
8.5.34
PAP Path CD Wait Time Register (address = 0x2C) [reset = 0x0000]
Table 81.
PAP_WAIT_CD Field Descriptions
8.5.35
PAP path AB Configuration Register (address = 0x2D) [reset = 0x0FFF]
Table 82.
PAP_CFG_AB Field Descriptions
8.5.36
PAP path CD Configuration Register (address = 0x2E) [reset = 0x0FFF]
Table 83.
PAP_CFG_CD Field Descriptions
8.5.37
DAC SPI Configuration Register (address = 0x2F) [reset = 0x0000]
Table 84.
SPIDAC_TEST1 Field Descriptions
8.5.38
DAC SPI Constant Register (address = 0x30) [reset = 0x0000]
Table 85.
SPIDAC_TEST2 Field Descriptions
8.5.39
Gain for path AB Register (address = 0x32) [reset = 0x0400]
Table 86.
GAINAB Field Descriptions
8.5.40
Gain for path CD Register (address = 0x33) [reset = 0x0400]
Table 87.
GAINCD Field Descriptions
8.5.41
JESD Error Counter Register (address = 0x41) [reset = 0x0000]
Table 88.
JESD_ERR_CNT Field Descriptions
8.5.42
JESD ID 1 Register (address = 0x46) [reset = 0x0044]
Table 89.
JESD_ID1 Field Descriptions
8.5.43
JESD ID 2 Register (address = 0x47) [reset = 0x190A]
Table 90.
JESD ID 2 Register (JESD_ID2)
8.5.44
JESD ID 3 and Subclass Register (address = 0x48) [reset = 0x31C3]
Table 91.
JESD_ID3 Field Descriptions
8.5.45
JESD Lane Enable Register (address = 0x4A) [reset = 0x0003]
Table 92.
JESD_LN_EN Field Descriptions
8.5.46
JESD RBD Buffer and Frame Octets Register (address = 0x4B) [reset = 0x1300]
Table 93.
JESD_RBD_F Field Descriptions
8.5.47
JESD K and L Parameters Register (address = 0x4C) [reset = 0x1303]
Table 94.
JESD_K_L Field Descriptions
8.5.48
JESD M and S Parameters Register (address = 0x4D) [reset = 0x0100]
Table 95.
JESD_M_S Field Descriptions
8.5.49
JESD N, HD and SCR Parameters Register (address = 0x4E) [reset = 0x0F4F]
Table 96.
JESD_N_HD_SCR Field Descriptions
8.5.50
JESD Character Match and Other Register (address = 0x4F) [reset = 0x1CC1]
Table 97.
JESD_MATCH Field Descriptions
8.5.51
JESD Link Configuration Data Register (address = 0x50) [reset = 0x0000]
Table 98.
JESD_Link_CFG Field Descriptions
8.5.52
JESD Sync Request Register (address = 0x51) [reset = 0x00FF]
Table 99.
JESD_SYNC_REQ Field Descriptions
8.5.53
JESD Error Output Register (address = 0x52) [reset = 0x00FF]
Table 100.
JESD_ERR_OUT Field Descriptions
8.5.54
JESD ILA Check 1 Register (address = 0x53) [reset = 0x0100]
Table 101.
JESD_ILA_CFG1 Field Descriptions
8.5.55
JESD ILA Check 2 Register (address = 0x54) [reset = 0x8E60]
Table 102.
JESD_ILA_CFG2 Field Descriptions
8.5.56
JESD SYSREF Mode Register (address = 0x5C) [reset = 0x0001]
Table 103.
JESD_SYSR_MODE Field Descriptions
8.5.57
JESD Crossbar Configuration 1 Register (address = 0x5F) [reset = 0x0123]
Table 104.
JESD_CROSSBAR1 Field Descriptions
8.5.58
JESD Crossbar Configuration 2 Register (address = 0x60) [reset = 0x4567]
Table 105.
JESD_CROSSBAR2 Field Descriptions
8.5.59
JESD Alarms for Lane 0 Register (address = 0x64) [reset = 0x0000]
Table 106.
JESD_ALM_L0 Field Descriptions
8.5.60
JESD Alarms for Lane 1 Register (address = 0x65) [reset = 0x0000]
Table 107.
JESD_ALM_L1 Field Descriptions
8.5.61
JESD Alarms for Lane 2 Register (address = 0x66) [reset = 0x0000]
Table 108.
JESD_ALM_L2 Field Descriptions
8.5.62
JESD Alarms for Lane 3 Register (address = 0x67) [reset = 0x0000]
Table 109.
JESD_ALM_L3 Field Descriptions
8.5.63
JESD Alarms for Lane 4 Register (address = 0x68) [reset = 0x0000]
Table 110.
JESD_ALM_L4 Field Descriptions
8.5.64
JESD Alarms for Lane 5 Register (address = 0x69) [reset = 0x0000]
Table 111.
JESD_ALM_L5 Field Descriptions
8.5.65
JESD Alarms for Lane 6 Register (address = 0x6A [reset = 0x0000]
Table 112.
JESD_ALM_L6 Field Descriptions
8.5.66
JESD Alarms for Lane 7 Register (address = 0x6B) [reset = 0x0000]
Table 113.
JESD Alarms for Lane 7 Register (JESD_ALM_L7)
8.5.67
SYSREF and PAP Alarms Register (address = 0x6C) [reset = 0x0000]
Table 114.
ALM_SYSREF_PAP Field Descriptions
8.5.68
Clock Divider Alarms 1 Register (address = 0x6D) [reset = 0x0000]
Table 115.
ALM_CLKDIV1 Field Descriptions
8.5.69
Clock Configuration Register (address = 0x0A) [reset = 0xFC03]
Table 116.
CLK_CONFIG Field Descriptions
8.5.70
Sleep Configuration Register (address = 0x0B) [reset = 0x0022]
Table 117.
SLEEP_CONFIG Field Descriptions
8.5.71
Divided Output Clock Configuration Register (address = 0x0C) [reset = 0x2002]
Table 118.
CLK_OUT Field Descriptions
8.5.72
DAC Fullscale Current Register (address = 0x0D) [reset = 0xF000]
Table 119.
DACFS Field Descriptions
8.5.73
Internal SYSREF Generator Register (address = 0x10) [reset = 0x0000]
Table 120.
LCMGEN Field Descriptions
8.5.74
Counter for Internal SYSREF Generator Register (address = 0x11) [reset = 0x0000]
Table 121.
LCMGEN_DIV Field Descriptions
8.5.75
SPI SYSREF for Internal SYSREF Generator Register (address = 0x12) [reset = 0x0000]
Table 122.
LCMGEN_SPISYSREF Field Descriptions
8.5.76
Digital Test Signals Register (address = 0x1B) [reset = 0x0000]
Table 123.
DTEST Field Descriptions
8.5.77
Sleep Pin Control Register (address = 0x23) [reset = 0xFFFF]
Table 124.
SLEEP_CNTL Field Descriptions
8.5.78
SYSREF Capture Circuit Control Register (address = 0x24) [reset = 0x1000]
Table 125.
SYSR_CAPTURE Field Descriptions
8.5.79
Clock Input and PLL Configuration Register (address = 0x31) [reset = 0x0200]
Table 126.
Clock Input and PLL Configuration Register (CLK_PLL_CFG)
8.5.80
PLL Configuration 1 Register (address = 0x32) [reset = 0x0308]
Table 127.
CONFIG1 Field Descriptions
8.5.81
PLL Configuration 2 Register (address = 0x33) [reset = 0x4018]
Table 128.
PLL_CONFIG2 Field Descriptions
8.5.82
LVDS Output Configuration Register (address = 0x34) [reset = 0x0000]
Table 129.
LVDS_CONFIG Field Descriptions
8.5.83
Fuse Farm clock divider Register (address = 0x35) [reset = 0x0018]
Table 130.
PLL_FDIV Field Descriptions
8.5.84
Serdes Clock Configuration Register (address = 0x3B) [reset = 0x1802]
Table 131.
SRDS_CLK_CFG Field Descriptions
8.5.85
Serdes PLL Configuration Register (address = 0x3C) [reset = 0x8228]
Table 132.
SRDS_PLL_CFG Field Descriptions
8.5.86
Serdes Configuration 1 Register (address = 0x3D) [reset = 0x0x0088]
Table 133.
RDS_CFG1 Field Descriptions
8.5.87
Serdes Configuration 2 Register (address = 0x3E) [reset = 0x0x0909]
Table 134.
SRDS_CFG2 Field Descriptions
8.5.88
Serdes Polarity Control Register (address = 0x3F) [reset = 0x0000]
Table 135.
SRDS_POL Field Descriptions
8.5.89
JESD204B SYNCB OUTPUT Register (address = 0x76) [reset = 0x0000]
Table 136.
SYNCBOUT Field Descriptions
9
Application and Implementation
9.1
Application Information
9.1.1
Start-up Sequence
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Calculating the JESD204B SerDes rate
9.2.4
Calculating valid JESD204B SYSREF Frequency
9.2.5
Application Curves
10
Power Supply Recommendations
10.1
Power Supply Sequencing
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Related Links
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
AAV|144
MPBGAM2C
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slasea6d_oa
slasea6d_pm
11
Layout