SLASEA6D February 2017 – June 2020 DAC38RF82 , DAC38RF89
PRODUCTION DATA.
In PLL bypass mode a high quality clock is sourced to the DACCLK inputs. This clock is used to directly clock the DAC38RF82 (or DAC38RF89) DAC cores. This mode gives the device best performance and is recommended for extremely demanding applications.
The bypass mode is selected by setting the following: