7.3.1 Serdes Input

The RX [7:0]P/N differential inputs are each internally terminated to a common point via 50Ω, as shown in
Figure 55.

Figure 55. Serial Lane Input Termination

Common mode termination is via a 50pF capacitor to GND. The common mode voltage and termination of the differential signal can be controlled in a number of ways to suit a variety of applications via rw_cfgrx0 [10:8] (TERM), as described in Table 1.
(Note: AC coupling is recommended for JESD204B compliance.)

Data input is sampled by the differential sensing amplifier using clocks derived from the clock recovery algorithm. The polarity of RXP and RXN can be inverted by setting the INVPAIR [7:0] bit of the corresponding lane to “1”. This can potentially simplify PCB layout and improve signal integrity by avoiding the need to swap over the differential signal traces.

Due to processing effects, the devices in the RXP and RXN differential sense amplifiers will not be perfectly matched and there will be some offset in switching threshold. DAC39J84 contains circuitry to detect and correct for this offset. This feature can be enabled by setting the rw_cfgrx0 [23] (ENOC) bit to “1”. It is anticipated the most users will enable this feature. During the compensation process, rw_cfgrx0 [25:24] (LOOPBACK) bit must be set to “00”.

7.3.2 Serdes Rate

DAC39J84 has 8 configurable JESD204B serial lanes. The highest speed of each SerDes lane is 12.5Gbps. Because the primary operating frequency of the SerDes is determined by its reference clock and PLL multiplication factor, there is a limit on the lowest SerDes rate supported, refer to Table 2 for details. To support lower speed application, each receiver should be configured to operate at half, quarter or eighth of the full rate via rw_cfgrx0 [6:5] (RATE).

7.3.3 Serdes PLL

DAC39J84 has two integrated PLLs, one PLL is to provide the clocking of DAC, which will be discussed in a DAC PLL section; the other PLL is to provide the clocking for the high speed SerDes. The reference frequency of the SerDes PLL can be in the range of 100-800MHz nominal, and 300-800MHz optimal.

The reference frequency is derived from DACCLK divided down based on the serdes_refclk_div programming, as shown in Figure 56.

Figure 56. Reference Clock of SerDes PLL

During normal operation, the clock generated by PLL will be 4-25 times the reference frequency, according to the multiply factor selected via rw_cfgpll [8:1] (MPY). In order to select the appropriate multiply factor and refclkp/n frequency, it is first necessary to determine the required PLL output clock frequency. The relationship between the PLL output clock frequency and the lane rate is shown in Table 3. Having computed the PLL output frequency, the reference frequency can be obtained by dividing this by the multiply factor specified via MPY.

The wide range of multiply factors combined with the different rate modes means it will often be possible to achieve a given line rate from multiple different reference frequencies. The configuration which utilizes the highest reference frequency achievable is always preferable.

The SerDes PLL VCO must be in the nominal range of 1.5625 - 3.125 GHz. It is necessary to adjust the loop filter depending on the operating frequency of the VCO. To indicate the selection the user must set the rw_cfgpll [9] (VRANGE) bit. If the PLL output frequency is below 2.17GHz, VRANGE should be set high.

Performance of the integrated PLL can be optimized according to the jitter characteristics of the reference clock by setting the appropriate loop bandwidth via rw_cfgpll [12:11] (LB) bits. The loop bandwidth is obtained by dividing the reference frequency by BWSCALE, where the BWSCALE is a function of both LB and PLL output frequency as shown in Table 5.

An approximate loop bandwidth of 8–30MHz is suitable and recommended for most systems where the reference clock is via low jitter clock input buffer. For systems where the reference clock is via a low jitter input cell, but of low quality, an approximate loop bandwidth of less than 8MHz may offer better performance. For systems where the reference clock is cleaned via an ultra low jitter LC-based cleaner PLL, a high loop bandwidth up to 60MHz is more appropriate. Note that the use of ultra high loop bandwidth setting is not recommended for PLL multiply factor of less than 8.

A free running clock output is available when rw_cfgpll [15:14] (ENDIVCLK) is set high. It runs at a fixed divided-by-5 of the PLL output frequency and has a duty cycle of 50%. A divided-by-16 of this free running clock can be configured to come out the alarm pin during digital test, see dtest [11:8] for the specific configuration needed.

7.3.4 Serdes Equalizer

All channels of the DAC39J84 incorporate an adaptive equalizer, which can compensate for channel insertion loss by attenuating the low frequency components with respect to the high frequency components of the signal, thereby reducing inter-symbol interference. Figure 57 shows the response of the equalizer, which can be expressed in terms of the amount of low frequency gain and the frequency up to which this gain is applied (i.e., the frequency of the ’zero’). Above the zero frequency, the gain increases at 6dB/octave until it reaches the high frequency gain.

Figure 57. Equalizer Frequency Response

The equalizer can be configured via rw_cfgrx0[21:19] (EQ) and rx_cfgrx0[22] (EQHLD). Table 6 and Table 7 summarize the options. When enabled, the receiver equalization logic analyzes data patterns and transition times to determine whether the low frequency gain should be increased or decreased. The decision logic is implemented as a voting algorithm with a relatively long analysis interval. The slow time constant that results reduces the probability of incorrect decisions but allows the equalizer to compensate for the relatively stable response of the channel. The lock time for the adaptive equalizer is data dependent, and so it is not possible to specify a generally applicable absolute limit. However, assuming random data, the maximum lock time will be 6x10⁶ divided by the CDR activity level. For CDR (rw_cfgrx0[18:16]) = 110, this is 1.5x10⁶UI.

When EQ[2] = 0, finer control of gain boost is available using the EQBOOSTi IEEE1500 tuning chain field, as shown in Table 8.

When EQ is set to 010 or 011, the equalizer is reconfigured to provide analytical data about the amount of pre and post cursor equalization respectively present in the received signal. This can in turn be used to adjust the equalization settings of the transmitting link partner, where a suitable mechanism for communicating this data back to the transmitter exists. Status information is provided viadtest[11:8] (EQOVER, EQUNDER), by using the following method:

1. Enable the equalizer by setting EQHLD low and EQ to 001. Allow sufficient time for the equalizer to adapt;
2. Set EQHLD to 1 to lock the equalizer and reset the adaption algorithm. This also causes both EQOVER and EQUNDER to become low;
3. Wait at least 48UI, and proportionately longer if the CDR activity is less than 100%, to ensure the 1 on EQHLD is sampled and acted upon;
4. Set EQ to 010 or 011, and EQHLD to 0. The equalization characteristics of the received signal are analysed (the equalizer response will continue to be locked);
5. Wait at least 150×10³UI to allow time for the analysis to occur, proportionately longer if the CDR activity is less than 100%;
6. Examine EQOVER and EQUNDER for results of analysis.
   • If EQOVER is high, it indicates the signal is over equalized;
   • If EQUNDER is high, it indicates the signal is under equalized;
7. Set EQHLD to 1;
8. Repeat items 3–7 if required;
9. Set EQ to 001, and EQHLD to 0 to exit analysis mode and return to normal adaptive equalization.

Note that when changing EQ from one non-zero value to another, EQHLD must already be 1. If this is not the case, there is a chance the equalizer could be reset by a transitory input state (i.e., if EQ is momentarily 000). EQHLD can be set to 0 at the same time as EQ is changed.

As the equalizer adaption algorithm is designed to equalize the post cursor, EQOVER or EQUNDER will only be set during post cursor analysis if the amount of post cursor equalization required is more or less than the adaptive equalizer can provide.

7.3.5 JESD204B Descrambler

The descrambler is a 16-bit parallel self-synchronous descrambler based on the polynomial 1 + x¹⁴ + x¹⁵. From the JESD204B specification, the scrambling/descrambling process only occurs on the user data, not on the code group synchronization or the ILA sequence. The descrambler output can be selected to sent out during JESD test, see jesd_testbus_sel for the specific configuration needed.

7.3.6 JESD204B Frame Assembly

The JESD204B defines the following parameters:

• L is the number of lanes per link
• M is the number of converters per device
• F is the number of octets per frame clock period
• S is the number of samples per frame
• HD is the High-Density bit which controls whether a sample may be divided over more lanes.

Table 9 and Table 10 list the available JESD204B formats for the DAC39J84. Table 11 lists the speed limits of the DAC39J84. The ranges are limited by the Serdes PLL VCO frequency range, the Serdes PLL reference clock range, the maximum Serdes line rate, and the maximum DAC sample frequency.

7.3.7 Serial Peripheral Interface (SPI)

The serial port of the DAC39J84 is a flexible serial interface which communicates with industry standard microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the operating modes of DAC39J84. It is compatible with most synchronous transfer formats and can be configured as a 3 or 4 pin interface by sif4_ena in register config2. In both configurations, SCLK is the serial interface input clock and SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data in and data out. For 4 pin configuration, SDIO is bidirectional and SDO is data out only. Data is input into the device with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK.

Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low. The first frame byte is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit address to be accessed. Table 12 indicates the function of each bit in the instruction cycle and is followed by a detailed description of each bit. The data transfer cycle consists of two bytes.

Figure 58 shows the serial interface timing diagram for a DAC39J84 write operation. SCLK is the serial interface clock input to DAC39J84. Serial data enable SDENB is an active low input to DAC39J84. SDIO is serial data in. Input data to DAC39J84 is clocked on the rising edges of SCLK.

Figure 58. Serial Interface Write Timing Diagram

Figure 59 shows the serial interface timing diagram for a DAC39J84 read operation. SCLK is the serial interface clock input to DAC39J84. Serial data enable SDENB is an active low input to DAC39J84. SDIO is serial data in during the instruction cycle. In 3 pin configuration, SDIO is data out from the DAC39J84 during the data transfer cycle, while SDO is in a high-impedance state. In 4 pin configuration, both SDIO and SDO are data out from the DAC39J84 during the data transfer cycle. At the end of the data transfer, SDIO and SDO will output low on the final falling edge of SCLK until the rising edge of SDENB when they will 3-state.

Figure 59. Serial Interface Read Timing Diagram

In the SIF interface there are four types of registers:

• NORMAL: The NORMAL register type allows data to be written and read from. All 16-bits of the data are registered at the same time. There is no synchronizing with an internal clock thus all register writes are asynchronous with respect to internal clocks. There are three subtypes of NORMAL:
  • AUTOSYNC: A NORMAL register that causes a sync to be generated after the write is finished. These are used when it is desirable to synchronize the block after writing the register or in the case of a single field that spans across multiple registers. For instance, the NCO requires three 16-bit register writes to set the frequency. Upon writing the last of these registers an autosync is generated to deliver the entire field to the NCO block at once, rather than in pieces after each invidiual register write. For a field that spans multiple registers, all non-AUTOSYNC registers for the field must be written first before the actual AUTOSYNC register.
  • No RESET Value: These are NORMAL registers, but the reset value cannot be guaranteed. This could be because the register has some read_only bits or some internal logic partially controls the bit values.
• READ_ONLY: Registers that can be read from but not written to.
• WRITE_TO_CLEAR: These registers are just like NORMAL registers with one exception. They can be written and read, however, when the internal logic asynchronously sets a bit high in one of these registers, that bit stays high until it is written to ‘0’. This way interrupts will be captured and stay constant until cleared by the user. In DAC39J84, register config100-108 are WRTE_TO_CLEAR registers.

7.3.8 Multi-Device Synchronization

In many applications, such as multi antenna systems where the various transmit channels information is correlated, it is required that the latency across the link is deterministic and multiple DAC devices are completely synchronized such that their outputs are phase aligned. DAC39J84 achieves the deterministic latency using SYSREF (JESD204B Subclass 1).

SYSREF is generated from the same clock domain as DACCLK, and is sampled at the rising edges of the device clock. It can be periodic, single-shot or “gapped” periodic. After having resynchronized its local multiframe clock (LMFC) to SYSREF, the DAC will request a link re-initialization via SYNC interface. Processing of the signal on the SYSREF input can be enabled and disabled via the SPI interface.

7.3.9 Input Multiplexer

The DAC39J84 includes a multiplexer after the JESD204B interface that allows any input stream A-B to be routed to any signal cannel A-B. See pathx_in_sel for details on how to configure the cross-bar switches.

7.3.10 FIR Filters

Figure 60 through Figure 63 show the magnitude spectrum response for the FIR0, FIR1, FIR2 and FIR3 interpolating filters where f_IN is the input data rate to the FIR filter. Figure 64 to Figure 67 show the composite filter response for 2x, 4x, 8x and 16x interpolation. The transition band for all interpolation settings is from 0.4 to 0.6 x f_DATA (the input data rate to the device) with < 0.001dB of pass-band ripple and > 90 dB stop-band attenuation.

The DAC39J84 includes a no interpolation 1x mode. However, the input data rate in this mode is limited to 1250MSPS. See more details in Table 11.

The DAC39J84 also has a 9-tap inverse sinc filter (FIR4) that runs at the DAC update rate (f_DAC) that can be used to flatten the frequency response of the sample-and-hold output. The DAC sample-and-hold output sets the output current and holds it constant for one DAC clock cycle until the next sample, resulting in the well-known sin(x)/x or sinc(x) frequency response (Figure 68, red line). The inverse sinc filter response (Figure 68, blue line) has the opposite frequency response from 0 to 0.4 x F_dac, resulting in the combined response (Figure 68, green line). Between 0 to 0.4 x f_DAC, the inverse sinc filter compensates the sample-and-hold roll-off with less than 0.03 dB error.

The inverse sinc filter has a gain > 1 at all frequencies. Therefore, the signal input to FIR4 must be reduced from full scale to prevent saturation in the filter. The amount of back-off required depends on the signal frequency, and is set such that at the signal frequencies the combination of the input signal and filter response is less than 1 (0 dB). For example, if the signal input to FIR4 is at 0.25 x f_DAC, the response of FIR4 is 0.9 dB, and the signal must be backed off from full scale by 0.9 dB to avoid saturation. The gain function in the QMC blocks can be used to reduce the amplitude of the input signal. The advantage of FIR4 having a positive gain at all frequencies is that the user is then able to optimize the back-off of the signal based on its frequency.

The filter taps for all digital filters are listed in Table 14. Note that the loss of signal amplitude may result in lower SNR due to decrease in signal amplitude.

Figure 60. Magnitude Spectrum for FIR0

Figure 61. Magnitude Spectrum for FIR1

Figure 62. Magnitude Spectrum for FIR2

Figure 64. 2x Interpolation Composite Response

Figure 66. 8x Interpolation Composite Response

Figure 68. Magnitude Spectrum for Inverse Sinc Filter

Figure 63. Magnitude Spectrum for FIR3

Figure 65. 4x Interpolation Composite Response

Figure 67. 16x Interpolation Composite Response

7.3.11 Full Complex Mixer

The DAC39J84 has two full complex mixer (FMIX) blocks with independent Numerically Controlled Oscillators (NCO) that enables flexible frequency placement without imposing additional limitations in the signal bandwidth. The NCOs have 48-bit frequency registers (phaseaddab(47:0) and phaseaddcd(47:0)) and 16-bit phase registers (phaseoffsetab(15:0) and phaseoffsetcd(15:0)) that generate the sine and cosine terms for the complex mixing. The NCO block diagram is shown in Figure 69.

Figure 69. NCO Block Diagram

Synchronization of the NCOs occurs by resetting the NCO accumulators to zero. The synchronization source is selected by syncsel_NCO(3:0) in config31. The frequency word in the phaseaddab(47:0) and phaseaddcd(47:0) registers is added to the accumulators every clock cycle, f_DAC. The output frequency of the NCO is

Treating the two complex channels in the DAC39J84 as complex vectors of the form I + j Q, the output of FMIX I_OUT(t) and Q_OUT(t) is

I_OUT(t) = (I_IN(t)cos(2πf_NCOt + δ) – Q_IN(t)sin(2πf_NCOt + δ)) x 2^{(mixer_gain – 1)}

Q_OUT(t) = (I_IN(t)sin(2πf_NCOt + δ) + Q_IN(t)cos(2π f_NCOt + δ)) x 2^{(mixer_gain – 1)}

where t is the time since the last resetting of the NCO accumulator, δ is the phase offset value and mixer_gain is either 0 or 1. δ is given by:

δ = 2π × phase_offsetAB/CD(15:0)/2¹⁶

A block diagram of the mixer is shown in Figure 70. The complex mixer can be used as a digital quadrature modulator with a real output simply by only using the I_OUT branch and ignoring the Q_OUT branch.

Figure 70. Complex Mixer Block Diagram

The maximum output amplitude of FMIX occurs if I_IN(t) and Q_IN(t) are simultaneously full scale amplitude and the sine and cosine arguments are equal to 2π × f_NCOt + δ (2N-1) x π/4 (N = 1, 2, ...).

With mixer_gain = 0 in config2, the gain through FMIX is sqrt(2)/2 or –3 dB. This loss in signal power is in most cases undesirable, and it is recommended that the gain function of the QMC block be used to increase the signal by 3 dB to compensate. With mixer_gain = 1, the gain through FMIX is sqrt(2) or +3 dB, which can cause clipping of the signal if I_IN(t) and Q_IN(t) are simultaneously near full scale amplitude and should therefore be used with caution.

7.3.12 Coarse Mixer

In addition to the full complex mixers the DAC39J84 also has a coarse mixer block capable of shifting the input signal spectrum by the fixed mixing frequencies ±n × f_S/8. Using the coarse mixer instead of the full mixers will result in lower power consumption.

Treating the two complex channels as complex vectors of the form I(t) + j Q(t), the outputs of the coarse mixer, I_OUT(t) and Q_OUT(t) are equivalent to:

I_OUT(t) = I(t)cos(2πf_CMIXt) – Q(t)sin(2πf_CMIXt)

Q_OUT(t) = I(t)sin(2πf_CMIXt) + Q(t)cos(2πf_CMIXt)

where f_CMIX is the fixed mixing frequency selected by cmix=(fs8, fs4, fs2, fsm4). The mixing combinations are described in Table 14.

7.3.13 Dithering

DAC39J84 supports the addition of a band limited dither to the DAC output after the complex mixer. This feature is enabled by set dither_ena to “1” and can be useful in reducing the high order harmonics. The generated dithering sequence can be optionally up-converted to an offset of Fs/2 by setting dither_mixer_ena to “1”. The added dithering sequence has variable amplitude in 6 dB steps via dither_sra_sel.

7.3.14 Complex Summation

The DAC39J84 has a complex summation block which is to sum channel A with channel C, channel B with Channel D, and the resulted complex summation are divided by 2 and sent via channel A and channel B. This feature is enabled by set output_sum to “1” and can be useful for multi-band application.

7.3.15 Quadrature Modulation Correction (QMC)

7.3.15.1 Gain and Phase Correction

The DAC39J84 includes a Quadrature Modulator Correction (QMC) block. The QMC blocks provide a mean for changing the gain and phase of the complex signals to compensate for any I and Q imbalances present in an analog quadrature modulator. The block diagram for the QMC block is shown in Figure 71. The QMC block contains 3 programmable parameters.

Registers qmc_gaina/b(10:0) and qmc_gainc/d(10:0) controls the I and Q path gains and is an 11-bit unsigned value with a range of 0 to 1.9990 and the default gain is 1.0000. The implied decimal point for the multiplication is between bit 9 and bit 10. The resolution allows suppression to > 65 dBc for a frequency independent IQ imbalance (the fine delay FIR block also contains gain control through the filter taps or inverse gain block that allows control with > 20 bits resolution, which can be used to improve the sideband suppression).

Register qmc_phaseab/cd(11:0) control the phase imbalance between I and Q and are a 12-bit values with a range of –0.5 to approximately 0.49975. The QMC phase term is not a direct phase rotation but a constant that is multiplied by each "Q" sample then summed into the "I" sample path. This is an approximation of a true phase rotation in order to keep the implementation simple. The resolution of the phase term allows suppression to > 80 dBc for a frequency independent IQ imbalance.

LO feed-through can be minimized by adjusting the DAC offset feature described below.

Figure 71. QMC Block Diagram

7.3.15.2 Offset Correction

Registers qmc_offseta(12:0), qmc_offsetb(12:0), qmc_offsetc(12:0) and qmc_offsetd(12:0) can be used to independently adjust the DC offsets of each channel. The offset values are in represented in 2s-complement format with a range from –4096 to 4095. The LSB resolution of the offset allows LO suppression to better than 90 dBFS.

The offset value adds a digital offset to the digital data before digital-to-analog conversion. Since the offset is added directly to the data it may be necessary to back off the signal to prevent saturation. Both data and offset values are LSB aligned.

Figure 72. Digital Offset Block Diagram

7.3.16 Group Delay Correction Block

A complex transmitter system typically is consisted of a DAC, reconstruction filter network, and I/Q modulator. Besides the gain and phase mismatch contribution, there could also be timing mismatch contribution from each components. For instance, the timing mismatch could come from the PCB trace length variation between the I and Q channels and the group delay variation from the reconstruction filter. This timing mismatch in the complex transmitter system creates phase mismatch that varies linearly with respect to frequency. To compensate for the I/Q imbalances due to this mismatch, the DAC39J84 has group delay correction block for each DAC channel.

DAC39J84 incorporates 2 FIR filters for small fractional group delay and 4 FIR filters for large fractional group delay. The input data to this block consists of 2, complex data (I/Q) channels i.e. 4 buses of 16-bit data. Control bits from configuration registers select the data path for all inputs through this block. Each input can either go through the small fractional delay filter (while its conjugate part goes through the matched delay line) or bypass the small fractional delay sub-block completely (matched delay line is bypassed for the conjugate part). The input to the large fractional delay F can either come from the output of small fractional delay sub-block or the original input to the block. The large fractional delay sub-block can also be completely bypassed if desired.

DAC39J84 also include an integer delay block following each large fractional group delay filter, which can further delay the DAC output by [0-3]×Tdac. Channel A&B share the same control signal output_delayab, and channel C&D share the same control signal output_delaycd, which means that channel A&B have the same integer delay, and channel C&D have the same integer delay.

Figure 73. Diagram of Group Delay Correction

7.3.17 Output Multiplexer

The DAC39J84 includes an output multiplexer before the digital to analog converters that allows any signal channel A-D to be routed to any DAC A-D. See pathx_out_sel for details on how to configure the cross-bar switches.

7.3.18 Power Measurement And Power Amplifier Protection

DAC39J84 provides an optional mechanism to protect the Power Amplifier (PA) in cases when the signal power shows some abnormality. For example, if the data clock is lost, the FIFO would automatically generate a single tone signal, which causes abnormally high average power and could be dangerous to the PA. In the PA protection mechanism, the signal power is monitored by maintaining an sliding window accumulation of last N samples. N is selectable to be 64 or 128 based on the setting of pap_dlylen_sel. The average amplitude of input signal is computed by dividing accumulated value by the number of samples in the delay-line (N). The result is then compared against a threshold (pap_vth). If the threshold is violated, the delayed input signal is divided by a value chosen by pap_gain, to form a scaled down version of the input signal. Since PAP output derives from a delay-line, there is deterministic latency of at least N cycles from the block input to block output. The PA protection is enabled by setting the pap_ena bit to “1”.

Figure 74. Diagram of Power Measurement and PA Protection Mechanism

7.3.19 Serdes Test Modes

DAC39J84 supports a number of basic pattern generation and verification of SerDes via SIF. Three pseudo random bit stream (PRBS) sequences are available, along with an alternating 0/1 pattern and a 20-bit user-defined sequence. The 2⁷-1,2³¹-1 or 2²³-1 sequences implemented can often be found programmed into standard test equipment, such as a Bit Error Rate Tester (BERT). Pattern generation and verification selection is via the TESTPATT fields of rw_cfgrx0[14:12], as shown in Table 18.

Pattern verification compares the output of the serial to parallel converter with an expected pattern. When there is a mismatch, the TESTFAIL bit is driven high, which can be programmed to come out the ALARM pin by setting dtest[3:0] to “0011”.

DAC39J84 also provide a number of advanced diagnostic capabilities controlled by the IEEE 1500 interface. These are:

• Accumulation of pattern verification errors;
• The ability to map out the width and height of the receive eye, known as Eye Scan;
• Real-time monitoring of internal voltages and currents;

The SerDes blocks support the following IEEE1500 instructions:

The data for each SerDes instruction is formed by chaining together sub-components called head, body (receiver or transmitter) and tail. DAC39J84 uses two SerDes receiver blocks R0 and R1, each of which contains 4 receive lanes (channels), the data for each IEEE1500 instruction is formed by chaining {head, receive lane 0, receive lane 1, receive lane 2, receive lane 3, tail}. A description of bits in head, body and tail for each instruction is given as follows:

7.3.20 Error Counter

All receive channels include a 12-bit counter for accumulating pattern verification errors. This counter is accessible via the ECOUNT IEEE1500 Char field. It is an essential part of the eye scan capability (see next section), though can be used independently of this..

The counter increments once for every cycle that the TESTFAIL bit is detected. The counter will not increment when at its maximum value (i.e., all 1s). When an IEEE1500 capture is performed, the count value is loaded into the ECOUNT scan elements (so that it can be scanned out), and the counter is then reset, provided ENCOR is set high.

ECOUNT can be used to get a measure of the bit error rate. However, as the error rate increases, it will become less accurate due to limitations of the pattern verification capabilities. Specifically, the pattern verifier checks multiple bits in parallel (as determined by the Rx bus width), and it is not possible to distinguish between 1 or more errors in this.

7.3.21 Eye Scan

All receive channels provide features which facilitate mapping the received data eye or extracting a symbol response. A number of fields accessible via the IEEE1500 Char scan chain allow the required low level data to be gathered. The process of transforming this data into a map of the eye or a symbol response must then be performed externally, typically in software.

The basic principle used is as follows:

• Enable dedicated eye scan input samplers, and generate an error when the value sampled differs from the normal data sample;
• Apply a voltage offset to the dedicated eye scan input samplers, to effectively reduce their sensitivity;
• Apply a phase offset to adjust the point in the eye that the dedicated eye scan data samples are taken;
• Reset the error counter to remove any false errors accumulated as a result of the voltage or phase offset adjustments;
• Run in this state for a period of time, periodically checking to see if any errors have occurred;
• Change voltage and/or phase offset, and repeat.

Alternatively, the algorithm can be configured to optimize the voltage offset at a specified phase offset, over a specified time interval.

Eye scan can be used in both synchronous and asynchronous systems, while receiving normal data traffic. The IEEE1500 Char fields used to directly control eye scan and symbol response extraction are ES, ESWORD, ES BIT SELECT, ESLEN, ESPO, ESVO, ESVO OVR, ESRUN and ESDONE, see Table 23. Eye scan errors are accumulated in ECOUNT.

The required eyescan mode is selected via the ES field, as shown in Table 24. When enabled, only data from the bit position within the 20-bit word specified via ES BIT SELECT is analyzed. In other words, only eye scan errors associated with data output at this bit position will accumulate in ECOUNT. The maximum legal ES BIT SELECT is 10011.

When ES[3] = 0, the selected analysis runs continuously. However, when ES[3] = 1, only the number of qualified samples specified by ESLEN, as shown in Table 25. In this case, analysis is started by writing a 1 to ESRUN (it is not necessary to set it back to 0). When analysis completes, ESDONE will be set to 1.

When ESVO OVR = 1, the ESVO field determines the amount of offset voltage that is applied to the eye scan data samplers associated with rxpi and rxni. The amount of offset is variable between 0 and 300mV in increments of ~10mV, as shown in Table 26. When ES[3] = 1, ESVO OVR must be 0 to allow the optimized voltage offset to be read back via ESVO.

The phase position of the samplers associated with rxpi and rxni, is controlled to a precision of 1/32UI. When ES is not 00, the phase position can be adjusted forwards or backwards by more than one UI using the ESPO field, as shown in Table 27. In normal use, the range should be limited to ±0.5UI (+15 to –16 phase steps).

7.3.22 JESD204B Pattern Test

DAC39J84 supports the following test patterns for JESD204B:

• Link layer test pattern
  • Verify repeating /D.21.5/ high frequency pattern for random jitter (RJ)
  • Verify repeating /K.28.5/ mixed frequency pattern for deterministic jitter (DJ)
  • Verify repeating initial lane alignment (ILA) sequence
  • RPAT, JSPAT or JTSPAT pattern can be verified using errors counter of 8b/10b errors produced over an amount of time to get an estimate of BER.
• Transport layer test pattern: implements a short transport layer pattern check based on F = 1,2,4 or 8. The short test pattern has a duration of one frame period and is repeated continuously for the duration of the test. Refer to JESD204B standard section 5.1.6 for more details.
  • F = 1 : Looks for a constant 0xF1.
  • F = 2 : Each frame should consist of 0xF1, 0xE2
  • F = 4 : Looks for a constant 0xF1, 0xE2, 0xD3, 0xC4
  • F = 8 : Each frame should consist of 0xF1, 0xE2, 0xD3, 0xC4, 0xB5, 0xA6, 0x97, 0x80

Users can select to output the internal data (ex, the 8b/10 decoder output, comma alignment output, lane alignment output, frame alignment output, descrambler output, etc ) of a JESD link for test purpose. See jesd_test_seq for configuration details.

7.3.23 Temperature Sensor

The DAC39J84 incorporates a temperature sensor block which monitors the temperature by measuring the voltage across 2 transistors. The voltage is converted to an 8-bit digital word using a successive-approximation (SAR) analog to digital conversion process. The result is scaled, limited and formatted as a twos complement value representing the temperature in degrees Celsius.

The sampling is controlled by the serial interface signals SDENB and SCLK. If the temperature sensor is enabled (tsense_sleep = “0” in register config26) a conversion takes place each time the serial port is written or read. The data is only read and sent out by the digital block when the temperature sensor is read in memin_tempdata in config7. The conversion uses the first eight clocks of the serial clock as the capture and conversion clock, the data is valid on the falling eighth SCLK. The data is then clocked out of the chip on the rising edge of the ninth SCLK. No other clocks to the chip are necessary for the temperature sensor operation. As a result the temperature sensor is enabled even when the device is in sleep mode.

In order for the process described above to operate properly, the serial port read from config6 must be done with an SCLK period of at least 1 μs. If this is not satisfied the temperature sensor accuracy is greatly reduced.

7.3.24 Alarm Monitoring

The DAC39J84 includes a flexible set of alarm monitoring that can be used to alert of a possible malfunction scenario. All the alarm events can be accessed either through the SIP registers and/or through the ALARM pin. Once an alarm is set, the corresponding alarm bit in register configtbd must be reset through the serial interface to allow further testing. The set of alarms includes the following conditions:

• JESD alarms
  • multiframe alignment_error. Occurs when multiframe alignment fails.
  • frame alignment error. Occurs when frame alignment fails.
  • link configuration error. Occurs when configuration data in ILA sequence does not match programmed configuration.
  • elastic buffer overflow. Occurs when bad RBD value is used causing the elastic buffer to overflow.
  • elastic buffer match error. Occurs when the first non-/K/ doesn’t match the programmed character.
  • code synchronization error.
  • 8b/10b not-in-table decode error.
  • 8b/10 disparity error.
  • alarm_from_shorttest. Occurs when the JESD204B interface fails the short pattern test.
• SerDes alarms
  • memin_rw_losdct. Occurs when there are loss of signal detect from SerDes lanes.
  • FIFO write error. Occurs if write request and FIFO is full.
  • FIFO write full: Occurs if FIFO is full.
  • FIFO read error. Occurs if read request and FIFO is empty.
  • FIFO read empty: Occurs if FIFO is empty.
  • alarm_rw0_pll. Occurs if the PLL in the SerDes block for RX0 through RX3 goes out of lock.
  • alarm_rw1_pll. Occurs if the PLL in the SerDes block for RX4 through RX7 goes out of lock.
• SYSREF alarm
  • alarm_sysref_err. Occurs when the SYSREF is received at an unexpected time. If too many of these occur it will cause the JESD to go into synchronization mode again.
• DAC PLL alarm
  • alarm_from_pll. Occurs when the DAC PLL is out of lock. This alarm can be ignored if the DAC PLL is not being used.
• PAP alarms
  • alarm_pap. Occurs when the average power is above the threshold. While any alarm_pap is asserted the attenuation for the appropriate data path is applied.

7.3.25 LVPECL Inputs

Figure 75 shows an equivalent circuit for the DAC input clock (DACCLKP/N) and the SYSREF (SYSREFP/N).

Figure 75. DACCLKP/N and SYSREFP/N Equivalent Input Circuit

7.3.26 CMOS Digital Inputs

Figure 76 shows a schematic of the equivalent CMOS digital inputs of the DAC39J84. SDIO, SCLK, TCLK, SLEEP, TESTMODE and TXENABLE have pull-down resistors while SDENB, RESETB, TMS, TDI and TRSTB have pull-up resistors internal to the DAC39J84. See the specification table for logic thresholds. The pull-up and pull-down circuitry is approximately equivalent to 100kΩ.

Figure 76. CMOS Digital Equivalent Input

7.3.27 Reference Operation

The DAC39J84 uses a bandgap reference and control amplifier for biasing the full-scale output current. The full-scale output current is set by applying an external resistor R_BIAS to pin BIASJ. The bias current I_BIAS through resistor R_BIAS is defined by the on-chip bandgap reference voltage and control amplifier. The default full-scale output current equals 64 times this bias current and can thus be expressed as:

IOUT_FS = 16 x I_BIAS = 64 x V_EXTIO / R_BIAS

The DAC39J84 has a 4-bit coarse gain control coarse_dac(3:0) in the configtbd register. Using gain control, the IOUT_FS can be expressed as:

IOUT_FS = (coarse_dac + 1) /16 x I_BIAS x 64 = (coarse_dac + 1) /16 x V_EXTIO / R_BIAS x 64

where V_EXTIO is the voltage at pin EXTIO. The bandgap reference voltage delivers an accurate voltage of 0.9V. This reference is active when extref_ena = ‘0’ in configtbd. An external decoupling capacitor C_EXT of 0.1 µF should be connected externally to pin EXTIO for compensation. The bandgap reference can additionally be used for external reference operation. In that case, an external buffer with high impedance input should be applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference can be disabled and overridden by an external reference by setting the extref_ena control bit. Capacitor C_EXT may hence be omitted. pin EXTIO thus serves as either input or output node.

The full-scale output current can be adjusted from 30 mA down to 10 mA by varying resistor R_BIAS or changing the externally applied reference voltage.

7.3.28 Analog Outputs

The CMOS DACs consist of a segmented array of PMOS current sources, capable of sourcing a full-scale output current up to 30 mA. Differential current switches direct the current to either one of the complimentary output nodes IOUTP or IOUTN. Complimentary output currents enable differential operation, thus canceling out common mode noise sources (digital feed-through, on-chip and PCB noise), dc offsets, even order distortion components, and increasing signal output power by a factor of four.

The full-scale output current is set using external resistor R_BIAS in combination with an on-chip bandgap voltage reference source (+0.9 V) and control amplifier. Current I_BIAS through resistor R_BIAS is mirrored internally to provide a maximum full-scale output current equal to 16 times I_BIAS.

The relation between IOUTP and IOUTN can be expressed as:

IOUT_FS = IOUTP + IOUTN

We will denote current flowing into a node as –current and current flowing out of a node as +current. Since the output stage is a current source the current flows from the IOUTP and IOUTN pins. The output current flow in each pin driving a resistive load can be expressed as:

IOUTP = IOUT_FS x CODE / 65536

IOUTN = IOUT_FS x (65535 – CODE) / 65536

where CODE is the decimal representation of the DAC data input word.

For the case where IOUTP and IOUTN drive resistor loads R_L directly, this translates into single ended voltages at IOUTP and IOUTN:

VOUTP = IOUT1 x R_L

VOUTN = IOUT2 x R_L

Assuming that the data is full scale (65535 in offset binary notation) and the R_L is 25 Ω, the differential voltage between pins IOUTP and IOUTN can be expressed as:

VOUTP = 20mA x 25 Ω = 0.5 V

VOUTN = 0mA x 25 Ω = 0 V

VDIFF = VOUTP – VOUTN = 0.5V

Note that care should be taken not to exceed the compliance voltages at node IOUTP and IOUTN, which would lead to increased signal distortion.

7.3.29 DAC Transfer Function

The DAC39J84 can be easily configured to drive a doubly terminated 50 Ω cable using a properly selected RF transformer. Figure 77 and Figure 78 show the 50 Ω doubly terminated transformer configuration with 1:1 and 4:1 impedance ratio, respectively. Note that the center tap of the primary input of the transformer has to be grounded to enable a DC current flow. Applying a 20 mA full-scale output current would lead to a 0.5 Vpp for a 1:1 transformer and a 1 Vpp output for a 4:1 transformer. The low dc-impedance between IOUTP or IOUTN and the transformer center tap sets the center of the ac-signal to GND, so the 1 Vpp output for the 4:1 transformer results in an output between –0.5 V and +0.5 V.

Figure 77. Driving a Doubly Terminated 50 Ω Cable Using a 1:1 Impedance Ratio Transformer

Figure 78. Driving a Doubly Terminated 50 Ω Cable Using a 4:1 Impedance Ratio Transformer

7.4.1 Clocking Modes

The DAC39J84 has a single differential clock DACCLKN/P to clock the DAC cores and internal digital logic. The DAC39J84 DACCLK can be sourced directly or generated through an on-chip low-jitter phase-locked loop (PLL).

In those applications requiring extremely low noise it is recommended to bypass the PLL and source the DAC clock directly from a high-quality external clock to the DACCLK input. In most applications system clocking can be simplified by using the on-chip PLL to generate the DAC core clock while still satisfying performance requirements. In this case the DACCLK pins are used as the reference frequency input to the PLL.

7.4.1.2 PLL Mode

In this mode the clock at the DACCLK input functions as a reference clock source to the on-chip PLL. The on-chip PLL will then multiply this reference clock to supply a higher frequency DAC cores clock. Figure 79 shows the block diagram of the PLL circuit, where N divider ratio ranges from 1 to 32, M divider ratio ranges from 1 to 256, and VCO prescaler divider from 2 to 18.

Figure 79. PLL Block Diagram

The DAC39J84 PLL mode is selected by setting the following:

1. pll_ena bit in register config49 to “1” to route to the PLL and clock path.
2. pll_sleep bit in register config26 to “0” to enable the PLL and VCO.

The output frequency of the VCO covers two frequency spans: H-band (4.44–5.6GHz) and L-band (3.7–4.66GHz). When pll_vcosel in register config51 is “1”, the L-band is selected; when pll_vcosel is “0”, the H-band is selected. At each band, the VCO range can be further adjusted by using the 6-bits pll_vco in register config51. Figure 80 shows a typical relationship between the PLL VCO coarse tuning bits pll_vco and the VCO center frequency. The corresponding equations for the H-band and L-band VCO are given in Equation 1 and Equation 2, respectively. Note that It is recommended to shift pll_vco by +1 to guarantee the VCO operation at hot temp environment. In case of cold temp environment, shift by -1 on the variable pll_vco is recommended.

Equation 1. H-Band: VCO Frequency (MHz) = 0.10998*pll_vco²+10.574*pll_vco+4446.3,

where pll_vcosel = "0" and pll_vcoitune = "11".

Equation 2. L-Band: VCO Frequency (MHz) = 0.089703*pll_vco²+8.8312*pll_vco+3752.5,

where pll_vcosel = "1" and pll_vcoitune = "10".

Figure 80. Typical PLL VCO Center Frequency vs Coarse Tuning Bits

Common wireless infrastructure frequencies are generated from this VCO frequency in conjunction with the pre-scaler setting pll_p in register config50 as shown in Table 28. When there are multiple valid VCO frequency and the pre-scaler settings to generate the same desired DACCLK frequency, higher pre-scaler divider ratio is recommended for better phase noise performance.

Table 28. VCO Operation

VCO FREQUENCY (MHz)	pll_vcosel	PRE-SCALE DIVIDER	DESIRED DACCLK (MHz)	pll_p(3:0)
4915.2	0	2	2457.6	0000
3932.16	1	2	1966.08	0000
4423.68	1	3	1474.56	0001
4915.2	0	4	1228.8	0010
4915.2	0	5	983.04	0011
5160.96	0	7	737.28	0101
4915.2	0	8	614.4	0110
4915.2	0	10	491.52	0111

The M divider is used to determine the phase-frequency-detector (PFD) and charge-pump (CP) frequency.

Table 29. PFD and CP Operation

DACCLK FREQUENCY (MHz)	M DIVIDER	PFD UPDATE RATE (MHz)	pll_m(7:0)
1474.56	12	122.88	00001011
1474.56	24	61.44	00010111
1474.56	48	30.72	00101111
1474.56	64	15.36	00111111

The N divider in the loop allows the PFD to operate at a lower frequency than the reference clock.

The overall divide ratio inside the loop is the product of the Pre-Scale and M dividers (P*M). The 5-bit pll_cp_adj is to set the charge pump current from 0 to 1.55mA with a step of 50µA. In nominal condition, if vco runs at 5GHz with P-ratio and M-ratio set as 2 and 4, the DACCLK frequency would be 2.5GHz and PFD frequency 625MHz. This needs 600µA charge pump current to stabilize the loop and gives the optimized phase noise performance. When P*M ratio increases, the charge pump current needs to be increased accordingly to sustain enough phase margin for the loop. By tuning the charge pump current, a wide range of PM ratio can be supported with the internal loop filter. In very extreme cases when the P*M ratio is huge (ex. PFD frequency of 10MHz, VCO frequency of 4GHz) and the loop cannot be stabilized even with the largest charge pump current, an external loop filter is required.

If an external filter is required, the following filter should be connected to the LPF pin (C9):

Figure 81. Recommended External Loop Filter

7.4.2 PRBS TEST MODE

DAC39J84 supports three types of PRBS sequences (2⁷-1, 2²³-1, and 2³¹-1) to verify the SerDes via SIF. To run the PRBS test on the DAC, users first need to setup the DAC for normal use, then make the following SPI writes:

1. config74, set bits 4:0 to 0x1E to disable JESD clock.
2. config61, set bits 14:12 to 0x2 to enable the 7-bit PRBS test pattern; or set bits 14:12 to 0x3 to enable the 23-bit PRBS test pattern; or set bits 14:12 to 0x4 to enable the 31-bit PRBS test pattern.
3. config27, set bits 11:8 to 0x3 to output PRBS testfail on ALARM pin.
4. config27, set bits 14:12 to the lane to be tested (0 through 7).
5. config62, make sure bits 12:11 are set to 0x0 to disable character alignment.

Users should monitor the ALARM pin to see the results of the test. If the test is failing, ALARM will be high (or toggling if marginal). If the test is passing, the ALARM will be low.

Table 30. Register Map

7.5.1 Register Descriptions

7.5.1.4 config3 Register – Address: 0x03, Default: 0xF380

Figure 85. config3 Register Format

15	14	13	12	11	10	9	8
coarse_dac				reserved	reserved	reserved	reserved
7	6	5	4	3	2	1	0
fifo_error_zeros_data_ena	reserved	reserved	reserved	reserved	reserved	reserved	sif_ txenable

Table 34. config3 Register Field Descriptions

Register Name	Addr (Hex)	Bit	Name	Function	Default Value
config3	0x3	15:12	coarse_dac	Scales the output current in 16 equal steps.	1111
		11:8	reserved	Reserved	0011
		7	fifo_error_zeros_data_ena	When asserted SerDes FIFO errors zero the data out of the JESD block.	1
		6:1	reserved	Reserved	000000
		0	sif_ txenable	When asserted the internal value of TXENABLE is ‘1’.	0