The SYSREF Windowing block is used to first detect the position of SYSREF relative to the input clock CLK± rising edge. Based on the window information, an optimum SYSREF sampling time is selected to maximize setup and hold timing margins relative to the input clock. In many cases, a single SYSREF sampling position SYSREF_SEL is sufficient to meet timing for all systems (device-to-device variation) and conditions (temperature and voltage variations). However, this feature can also be used by the system to expand the timing window by tracking the movement of SYSREF as operating conditions change or to remove system-to-system variation at production test by finding a unique optimal value at nominal conditions for each system.

This section describes proper usage of the SYSREF Windowing block (SYSREF_RECV_SLEEP must be programmed to 0). First, apply the device clock and SYSREF to the device. The location of SYSREF relative to the device clock cycle is determined and stored in the SYSREF_POS field. Each bit of SYSREF_POS represents a potential SYSREF sampling position. If a bit in SYSREF_POS is set to 1, then the corresponding SYSREF sampling position has a potential setup or hold violation. Upon determining the valid SYSREF sampling positions (the positions of SYSREF_POS that are set to 0) the desired sampling position can be chosen by setting SYSREF_SEL to the value corresponding to that SYSREF_POS position. In general, the middle sampling position between two setup and hold instances is chosen. The determination of SYSREF_SEL is performed at the nominal operating conditions of the system (temperature and supply voltage) to provide maximum margin for operating condition variations. This process can be performed at final test and the optimal SYSREF_SEL setting can be stored for use at every system power up. Further, SYSREF_POS can be used to characterize the skew between CLK± and SYSREF± over operating conditions for a system by sweeping the system temperature and supply voltages. For systems that have large variations in CLK± to SYSREF± skew, this characterization can be used to track the optimal SYSREF sampling position as system operating conditions change. In general, a single value can be found that meets timing over all conditions for well-matched systems, such as those where CLK± and SYSREF± come from a single clocking device.

The step size between each SYSREF_POS sampling position can be adjusted using SYSREF_ZOOM. When SYSREF_ZOOM is set to 0, the delay steps are coarser. When SYSREF_ZOOM is set to 1, the delay steps are finer. See the electrical specifications table for delay step sizes when SYSREF_ZOOM is enabled and disabled. In general, SYSREF_ZOOM is recommended to always be used (SYSREF_ZOOM = 1) unless a transition region (defined by 1's in SYSREF_POS) is not observed, which can be the case for low clock rates. Bits 0 and 19 of SYSREF_POS are always 1 because there is insufficient information to determine if these settings are close to a timing violation, although the actual valid window can extend beyond these sampling positions. The value programmed into SYSREF_SEL is the decimal number representing the desired bit location in SYSREF_POS. Table 7-4 lists some example SYSREF_POS readings and the optimal SYSREF_SEL settings. Although 20 sampling positions are provided by the SYSREF_POS status register, SYSREF_SEL only allows selection of the first 16 sampling positions, corresponding to SYSREF_POSbits 0 to 15. The additional SYSREF_POS status bits are intended only to provide additional knowledge of the SYSREF valid window. In general, lower values of SYSREF_SEL are selected because of delay variation over supply voltage, however in the fourth example a value of 14 provides additional margin and can be selected instead.

If SYSREF_PS_EN is set to 0, only the last SYSREF edge is used for the SYSREF_POS values. Setting SYSREF_PS_EN to 1 enables an "infinite persistence" mode, where if any SYSREF edge since SYSREF_PS_EN is enabled has a 1 in a position, the SYSREF_POS value is set to one. This provides worst case values for SYSREF_POS to select the optimum SYSREF_SEL setting.

To use SYSREF Windowing:

1. Apply SYSREF and CLK
2. Set SYSREF_RECV_SLEEP = 0 and SYSREF_ZOOM = 1
3. If persistence is desired, set SYSREF_PS_EN = 1 and allow many SYSREF transitions for SYSREF_POS to build.
4. Read SYSREF_POS and determine a proper setting for SYSREF_SEL, as shown above. If a proper sampling point cannot be determined, set SYSREF_ZOOM = 0 and retry.
5. Once a proper value for SYSREF_SEL is applied, program SYSREF_PROC_EN = 1 and SYSREF_ALIGN_EN = 1.
6. SYSREF is now being properly processed by the device and the user can proceed to use the JESD204C interface (or other functionality) that relies on SYSREF.
7. SYSREF may need to be adjusted over large temperature or supply voltage swings, depending on the input clock frequency. The SYSREF invalid window dependence on temperature (t_INV(TEMP)) and VA11 supply voltage (t_INV(VA11)) is given in Section 6.8. To adjust SYSREF_SEL to track shifts in SYSREF relative to the input clock, the following steps can be looped (that is, in background during operation of the JESD204C link):
   1. If persistence is desired, clear and then set SYSREF_PS_EN, and allow many SYSREF transitions for the SYSREF_POS data to build.
   2. Read SYSREF_POS and determine a new value for SYSREF_SEL (but do not program it yet). The procedure to incrementally adjust SYSREF_SEL should prefer values that are closer to the previousSYSREF_SEL value rather than selecting the smallest valid SYSREF_SEL value. This helps make sure that the original valid window is selected and tracked rather than selecting a different window which would cause clock realignment to occur.
   3. Program SYSREF_PROC_EN = 0. Write the new SYSREF_SEL value, and then set SYSREF_PROC_EN = 1. The new SYSREF_SEL value is now used by the device.
   4. Wait for some period of time, then return to step 7a above.