SBAS932 March 2024 DAC39RF10-SEP , DAC39RF10-SP , DAC39RFS10-SEP , DAC39RFS10-SP
PRODMIX
There are several methods to power down or temporarily disable the DAC outputs. To prevent asymmetric aging of the device circuits, in some options a low level output from the DACs is maintained. Table 8-1 lists the options for sleep or disabling the DAC outputs.
The most power is saved in full power down, which is enable by setting the MODE register to 0x3. In this mode a low level output signal is maintained to prevent asymmetric aging. Returning to full operation from full power down takes 100's of microseconds.
One or both DAC outputs can be disabled by setting the corresponding MXMODE register to 0x6. This saves some power and the DAC outputs a low level signal to prevent asymmetric aging. If only one channel is disabled, low level spurs from the disabled channel can feed into the active channel, creating spurs around -80 dBFS.
The TX ENABLE function, either through the TXEN0/1 balls or TX_EN registers, provides a method to quickly disable the DAC output by forcing the digital code to 0 (midscale) (see Section 6.9 for the TX ENABLE latency). When the QUITE_TX_ENABLE register is 0, a low level signal is still maintained at the output to prevent saturation. When QUITE_TX_ENABLE is 1, if data independent DEM and Dither is enable, this prevents asymmetric aging. If DEM and dither are disabled or DEM is set to data dependent DEM, the DAC can degrade over the lifetime of the device if a significant faction of the lifetime is spent in this mode. The degradation is channel specific, only affecting the channel that is disabled.
Option | MXMODE | TX_EN | QUIET_TX_DISABLE | DEM | DITHER | Low level output | long term degradation | Power Savings |
---|---|---|---|---|---|---|---|---|
Device Full Power Down (MODE = 0b11) | - | - | - | - | - | yes | no | Most |
DAC disable | 6 | 1 | - | - | - | yes | no | Some |
TX Enable | any | 0 | 0 | - | - | yes | no | Least |
TX Enable | 0-5 | 0 | 1 | 0,1 | 0,1 | no | no | Least |
TX Enable | 0-5 | 0 | 1 | 2, 3 | 3 | no | yes | Least |
TX Enable | 6 | 0 | 1 | 0,1 | 0,1 | no | no | Least |
TX Enable | 6 | 0 | 1 | 2,3 | 3 | no | yes | Least |
When the DAC is in full power down, the common mode voltage at the DAC output during sleep needs to be maintained below 2V. For AC coupled outputs, the bias is usually provided by an inductor or a balun center tap to 1.8V which forces the common mode also to 1.8V. For DC coupled output, which are typically terminated through a resistor to a voltage above 1.8V (for example, 2.3V), sufficient DAC output current must be provided to reduce the common mode voltage to less than 2V. This is achieved by programming DACx_CBIAS_SLEEP (Address 0x724 bits 7:4 for DACA and Address 0x726 bits 7:4 for DACB) according to the following equation:
where: