The device has three supply voltages
and requires seven supply domains to achieve data sheet performance as shown in
Table 8-4.
Table 8-4 Recommended Power Supply
Domains
Voltage |
Supply Domain |
Device Supplies |
+1.8V |
VDDA |
VDDA18A, VDDA18B |
VDDIO |
VDDIO |
VDDCSR |
VDDCLK, VDDSYS, VDDR |
+1V |
VDDL |
VDDLA, VDDLB |
VDDCLK |
VDDCLK10 |
DVDD |
VDDDIG, VDDT, VDDDEA and VDDDEB |
-1.8V |
VEEx |
VEEAM18, VEEBM18 |
The recommended power supply is shown
in Figure 8-22 for -SP grade and Figure 8-23 for -SEP grade. The power-supply voltages must be low in noise and provide the
needed current to achieve rated device performance. A step down high-efficiency
switching converter is used first, followed by a second stage of regulation using
LDOs to provide switching noise reduction and improved voltage accuracy. The user
can also refer to the TI WEBENCH® Power Designer which
can be used to select and design the individual power supply elements as needed. The
recommended switching regulators for are:
- -SP Grade:
- TPS50601A-SP = +2.2V
for the VDDLA, VDDLB and VDDCCLK10 domains
- TPS50601A-SP = +3V
for the VDDA18A, VDDA18B, VDDIO, VDDSYS18, VDDR18 and VDDCLK18
domains
- TPS50601A-SP = +1V
for VDDDIG, VDDEA, VDDEB and VDDT
- TPS7H4011-SP = -4.2V
for VEEAM18 and VEEBM18 domains
- -SEP Grade:
- TPS7H4010-SEP = +2.2V
for the VDDLA, VDDLB and VDDCCLK10 domains
- TPS7H4010-SEP = +3V
for the VDDA18A, VDDA18B, VDDIO, VDDSYS18, VDDR18 and VDDCLK18
domains
- TPS7H4010-SEP = +1V
for VDDDIG, VDDEA, VDDEB and VDDT
- TPS7H4010-SEP = -3.3V
for VEEAM18 and VEEBM18 domains
and recommended LDOs include:
- -SP grade
- TPS7H1111-SP for
+1.8V and +1V
- TPS7A4501-SP for
-1.8V
- -SEP grade
- TPS7H1111-SEP for
+1.8V and +1V
- TPS7H1210-SEP for
-1.8V
The VDDA supply is regulated by an
LDO, or low-noise drop-out linear regulator, with a +1.8V output and is further
broken down into the following subgroup power domains:
- VDDA: VDDA18A, VDDA18B
- VDDIO
- VDDCSR: VDDCLK18, VDDSYS18,
VDDR18
Each device supply can be tied to a
single LDO but are isolated with a ferrite bead and/or three-terminal capacitor or
similar.
The VDDL supply is +1V and is further
broken down into VDDLA and VDDLB. Each device supply can be tied to a single LDO but
are isolated with a ferrite bead and/or three-terminal capacitor or similar.
The VDDCLK10 supply is +1V and is the
most sensitive for achieving the best phase noise performance. VDDCLK10 should be
isolated to a LDO by itself to prevent noise from other 1.0V supplies coupling into
the clock path.
The DVDD supply is +1V and can be
directly connected to a switching power supply. The DVDD encompasses the following
device supplies, VDDDIG10, VDDT, VDDEA and VDDEB, which can all be connected
together. No further isolation with a ferrite bead and/or three-terminal capacitor
or similar is required.
The VEEx supply is -1.8V derived from
a single LDO and is further broken down into VEEAM18 and VEEBM18, which are isolated
with a ferrite bead and/or three-terminal capacitor or similar.
It is also highly recommended to
follow these important power supply design considerations:
- Decouple all power supply rails
and bus voltages as they come onto the system board. Further place additional
decoupling at or near the DAC itself for each power domain. Typically, one
decoupling capacitor per power supply pin is suffice unless specified in the
data sheet or EVM assembly.
- Remember that approximately
20dB/decade noise suppression is gained for each additional filtering stage.
- Decouple for both high and low
frequencies, which might require multiple capacitor values.
- Series ferrite beads and feed
through capacitors are commonly used at the power plain entry point, and can be
used for addition power domain isolation. This should be done for each
individual supply voltage on the system board whether it comes from an LDO or a
switching regulator.
- For added capacitance, use
tightly stacked power and ground plane pairs (≤4 mil spacing) this adds inherent
high-frequency (>500MHz) decoupling to the PCB design.
- Keep supplies away from sensitive
analog circuitry such as the front-end RF stage of the DAC and high-speed
clocking and digital circuits if possible.
- Keep power domains that demand
higher currents, near the top of the stack-up or layer that has power plain
entry point. This minimizes the overall loop inductance.
- Any open or voided areas on power
plane, fill with ground to provide additional isolation and shielding.
- Keep a 20 to 25 mil gap between
all adjacent power and/or ground plane fills. This helps eliminate all gap
coupling between adjacent power domains and/or grounds within the same
layer.
- Some switcher regulator
circuitry/components could be located on the opposite side of the PCB for added
isolation.
- Follow the IC manufacture
recommendations; if the recommendations are not directly stated in an
application note or data sheet, then study the evaluation board. These are great
tools from which to learn. Applying the points listed above can help provide a
solid power supply design yielding data sheet performance in many
applications.
Each application has different
tolerances for noise on the supply voltage, so understanding these trades is best
described in the following two application notes for more details:
Also refer to Figure 8-31 through Figure 8-34 to illustrate the one power supply layout and stack-up approach.