SBAS932 March 2024 DAC39RF10-SEP , DAC39RF10-SP , DAC39RFS10-SEP , DAC39RFS10-SP
PRODMIX
The SYSREF input period must be an integer multiple of all clocks in the part, including the LMFC/LEMC. The following table depicts the requirements for the SYSREF period:
Requirements on SYSREF Period | Reason |
---|---|
SYSREF period must be a multiple of 16 CLK cycles. | DAC Encoder/DEM always operates with a FDAC/16 clock that is aligned to SYSREF. |
SYSREF period must be a multiple of LT CLK cycles This constraint does not apply to DDS mode (DDS_EN=1). | Makes sure the SYSREF period is a multiple of the input sample period. |
SYSREF period must be a multiple of 4*LT*S/F CLK cycles. This constraint does not apply to DDS mode (DDS_EN=1). | Makes sure the SYSREF period is a multiple of the effective link layer clock period. |
SYSREF period must be a multiple of LT*S*K CLK cycles. This constraint does not apply to Subclass 0 mode (SUBCLASS=0) or DDS mode (DDS_EN=1) | Makes sure that SYSREF period is a multiple of the LMFC/LEMC period. Note that K=256*E/F in 64b/66b mode. |