SBASAS1A November   2023  – March 2024 DAC39RF12 , DAC39RFS12

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI and FRI Timing Diagrams
    11. 6.11 Typical Characteristics: Bandwidth and DC Linearity
    12. 6.12 Typical Characteristics: Single Tone Spectra
    13. 6.13 Typical Characteristics: Dual Tone Spectra
    14. 6.14 Typical Characteristics: Noise Spectral Density
    15. 6.15 Typical Characteristics: Linearity Sweeps
    16. 6.16 Typical Characteristics: Modulated Waveforms
    17. 6.17 Typical Characteristics: Phase and Amplitude Noise
    18. 6.18 Typical Characteristics: Power Dissipation and Supply Currents
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 DES Mode
      2. 7.3.2 DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3 DEM and Dither
      4. 7.3.4 Offset Adjustment
      5. 7.3.5 Clocking Subsystem
        1. 7.3.5.1 SYSREF Frequency Requirements
        2. 7.3.5.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 7.3.6 Digital Signal Processing Blocks
        1. 7.3.6.1 Digital Upconverter (DUC)
          1. 7.3.6.1.1 Interpolation Filters
          2. 7.3.6.1.2 Numerically Controlled Oscillator (NCO)
            1. 7.3.6.1.2.1 Phase-Continuous NCO Update Mode
            2. 7.3.6.1.2.2 Phase-coherent NCO Update Mode
            3. 7.3.6.1.2.3 Phase-sync NCO Update Mode
            4. 7.3.6.1.2.4 NCO Synchronization
              1. 7.3.6.1.2.4.1 JESD204C LSB Synchonization
            5. 7.3.6.1.2.5 NCO Mode Programming
          3. 7.3.6.1.3 Mixer Scaling
        2. 7.3.6.2 Channel Bonder
        3. 7.3.6.3 DES Interpolator
      7. 7.3.7 JESD204C Interface
        1. 7.3.7.1  Deviation from JESD204C Standard
        2. 7.3.7.2  Transport Layer
        3. 7.3.7.3  Scrambler and Descrambler
        4. 7.3.7.4  Link Layer
        5. 7.3.7.5  Physical Layer
        6. 7.3.7.6  Serdes PLL Control
        7. 7.3.7.7  Serdes Crossbar
        8. 7.3.7.8  Multi-Device Synchronization and Deterministic Latency
          1. 7.3.7.8.1 Programming RBD
        9. 7.3.7.9  Operation in Subclass 0 Systems
        10. 7.3.7.10 Link Reset
      8. 7.3.8 Alarm Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 DUC and DDS Modes
      2. 7.4.2 JESD204C Interface Modes
        1. 7.4.2.1 JESD204C Interface Modes
        2. 7.4.2.2 JESD204C Format Diagrams
          1. 7.4.2.2.1 16-bit Formats
          2. 7.4.2.2.2 12-bit Formats
          3. 7.4.2.2.3 8-bit Formats
      3. 7.4.3 NCO Synchronization Latency
      4. 7.4.4 Data Path Latency
    5. 7.5 Programming
      1. 7.5.1 Using the Standard SPI Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Protocol
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 Using the Fast Reconfiguration Interface
      3. 7.5.3 SPI Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure for DUC/Bypass Mode
      2. 8.1.2 Startup Procedure for DDS Mode
      3. 8.1.3 Eye Scan Procedure
      4. 8.1.4 Pre/Post Cursor Analysis Procedure
      5. 8.1.5 Understanding Dual Edge Sampling Modes
      6. 8.1.6 Sleep and Disable Modes
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Transmitter Design Procedure
        1. 8.2.2.1 Detailed Clocking Subsystem Design Procedure
          1. 8.2.2.1.1 Example 1: SWAP-C Optimized
          2. 8.2.2.1.2 Example 2: Improved Phase Noise LMX2820 with External VCO
          3. 8.2.2.1.3 Example 3: Discrete Analog PLL for Best DAC Performance
          4. 8.2.2.1.4 12 GHz Clock Generation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines and Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.4.2.2.1 16-bit Formats
Table 7-24 JMODE 0 (16-bit, 16 lanes per stream, 1 stream)
Octet01
Nibble0123
Lane 0CH0_I[0]
Lane 1CH0_I[1]
Lane 2CH0_I[2]
Lane 3CH0_I[3]
Lane 4CH0_I[4]
Lane 5CH0_I[5]
Lane 6CH0_I[6]
Lane 7CH0_I[7]
Lane 8CH0_I[8]
Lane 9CH0_I[9]
Lane 10CH0_I[10]
Lane 11CH0_I[11]
Lane 12CH0_I[12]
Lane 13CH0_I[13]
Lane 14CH0_I[14]
Lane 15CH0_I[15]
Table 7-25 JMODE 1 (16-bit, 8 lanes per stream, 2 streams maximum)
Octet01
Nibble0123
Lane 0CH0_I[0]
Lane 1CH0_I[1]
Lane 2CH0_I[2]
Lane 3CH0_I[3]
Lane 4CH0_I[4]
Lane 5CH0_I[5]
Lane 6CH0_I[6]
Lane 7CH0_I[7]
Lane 8CH0_Q[0]
Lane 9CH0_Q[1]
Lane 10CH0_Q[2]
Lane 11CH0_Q[3]
Lane 12CH0_Q[4]
Lane 13CH0_Q[5]
Lane 14CH0_Q[6]
Lane 15CH0_Q[7]
Table 7-26 JMODE 2 (16-bit, 4 lanes per stream, 4 streams maximum)
Octet01
Nibble0123
Lane 0CH0_I[0]
Lane 1CH0_I[1]
Lane 2CH0_I[2]
Lane 3CH0_I[3]
Lane 4CH0_Q[0]
Lane 5CH0_Q[1]
Lane 6CH0_Q[2]
Lane 7CH0_Q[3]
Lane 8CH1_I[0]
Lane 9CH1_I[1]
Lane 10CH1_I[2]
Lane 11CH1_I[3]
Lane 12CH1_Q[0]
Lane 13CH1_Q[1]
Lane 14CH1_Q[2]
Lane 15CH1_Q[3]
Table 7-27 JMODE 3 (16-bit, 2 lanes per stream, 8 streams maximum)
Octet01
Nibble0123
Lane 0CH0_I[0]
Lane 1CH0_I[1]
Lane 2CH0_Q[0]
Lane 3CH0_Q[1]
Lane 4CH1_I[0]
Lane 5CH1_I[1]
Lane 6CH1_Q[0]
Lane 7CH1_Q[1]
Lane 8CH2_I[0]
Lane 9CH2_I[1]
Lane 10CH2_Q[0]
Lane 11CH2_Q[1]
Lane 12CH3_I[0]
Lane 13CH3_I[1]
Lane 14CH3_Q[0]
Lane 15CH3_Q[1]
Table 7-28 JMODE 4 (16-bit, 1 lane per stream, 8 streams maximum)
Octet01
Nibble0123
Lane 0CH0_I
Lane 1CH0_Q
Lane 2CH1_I
Lane 3CH1_Q
Lane 4CH2_I
Lane 5CH2_Q
Lane 6CH3_I
Lane 7CH3_Q
Table 7-29 JMODE 5 (16-bit, 1/2 lane per stream, 8 streams maximum)
Octet0123
Nibble01234567
Lane 0CH0_ICH0_Q
Lane 1CH1_ICH1_Q
Lane 2CH2_ICH2_Q
Lane 3CH3_ICH3_Q
Table 7-30 JMODE 6 (16-bit, 1/4 lane per stream, 8 streams maximum)
Octet01234567
Nibble0123456789101112131415
Lane 0CH0_ICH0_QCH1_ICH1_Q
Lane 1CH2_ICH2_QCH3_ICH3_Q
Table 7-31 JMODE 7 (16-bit, 1/8 lane per stream, 8 streams maximum)
Octet0123456789101112131415
Nibble012345678910111213141516171819202122232425262728293031
Lane 0CH0_ICH0_QCH1_ICH1_QCH2_ICH2_QCH3_ICH3_Q