SLASE30
October 2020
DAC43401-Q1
,
DAC53401-Q1
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements: I2C Standard Mode
7.7
Timing Requirements: I2C Fast Mode
7.8
Timing Requirements: I2C Fast Mode Plus
7.9
Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
7.10
Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
7.11
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Digital-to-Analog Converter (DAC) Architecture
8.3.1.1
Reference Selection and DAC Transfer Function
8.3.1.1.1
Power Supply as Reference
8.3.1.1.2
Internal Reference
8.3.2
DAC Update
8.3.2.1
DAC Update Busy
8.3.3
Nonvolatile Memory (EEPROM or NVM)
8.3.3.1
NVM Cyclic Redundancy Check
8.3.3.2
NVM_CRC_ALARM_USER Bit
8.3.3.3
NVM_CRC_ALARM_INTERNAL Bit
8.3.4
Programmable Slew Rate
8.3.5
Power-on-Reset (POR)
8.3.6
Software Reset
8.3.7
Device Lock Feature
8.3.8
PMBus Compatibility
8.4
Device Functional Modes
8.4.1
Power Down Mode
8.4.2
Continuous Waveform Generation (CWG) Mode
8.4.3
PMBus Compatibility Mode
8.5
Programming
8.5.1
F/S Mode Protocol
8.5.2
I2C Update Sequence
8.5.2.1
Address Byte
8.5.2.2
Command Byte
8.5.3
I2C Read Sequence
8.6
Register Map
8.6.1
STATUS Register (address = D0h) [reset = 000Ch or 0014h]
8.6.2
GENERAL_CONFIG Register (address = D1h) [reset = 01F0h]
8.6.3
TRIGGER Register (address = D3h) [reset = 0008h]
8.6.4
DAC_DATA Register (address = 21h) [reset = 0000h]
8.6.5
DAC_MARGIN_HIGH Register (address = 25h) [reset = 0000h]
8.6.6
DAC_MARGIN_LOW Register (address = 26h) [reset = 0000h]
8.6.7
PMBUS_OPERATION Register (address = 01h) [reset = 0000h]
8.6.8
PMBUS_STATUS_BYTE Register (address = 78h) [reset = 0000h]
8.6.9
PMBUS_VERSION Register (address = 98h) [reset = 2200h]
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
Programmable LED Biasing
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.3
Application Curves
9.2.2
Power-Supply Margining
9.2.2.1
Design Requirements
9.2.2.2
Detailed Design Procedure
9.2.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DSG|8
MPDS308C
Thermal pad, mechanical data (Package|Pins)
DSG|8
QFND141I
Orderable Information
slase30_oa
slase30_pm
12.6
Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.