SLASES7A July   2019  – December 2019 DAC43401 , DAC53401

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Functional Block Diagram
      2.      Power-Supply Control With the DACx3401
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2CTM Standard mode
    7. 7.7  Timing Requirements: I2CTM Fast mode
    8. 7.8  Timing Requirements: I2CTM Fast+ mode
    9. 7.9  Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
    10. 7.10 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 Reference Selection and DAC Transfer Function
          1. 8.3.1.1.1 Power Supply as Reference
          2. 8.3.1.1.2 Internal Reference
      2. 8.3.2 DAC Update
        1. 8.3.2.1 DAC Update Busy
      3. 8.3.3 Nonvolatile Memory (EEPROM or NVM)
        1. 8.3.3.1 NVM Cyclic Redundancy Check
        2. 8.3.3.2 NVM_CRC_ALARM_USER Bit
        3. 8.3.3.3 NVM_CRC_ALARM_INTERNAL Bit
      4. 8.3.4 Programmable Slew Rate
      5. 8.3.5 Power-on-Reset (POR)
      6. 8.3.6 Software Reset
      7. 8.3.7 Device Lock Feature
      8. 8.3.8 PMBus Compatibility
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Down Mode
      2. 8.4.2 Continuous Waveform Generation (CWG) Mode
      3. 8.4.3 PMBus Compatibility Mode
      4. 8.4.4 Medical Alarm Generation Mode
        1. 8.4.4.1 Low-Priority Alarm
        2. 8.4.4.2 Medium-Priority Alarm
        3. 8.4.4.3 High-Priority Alarm
        4. 8.4.4.4 Interburst Time
        5. 8.4.4.5 Pulse Off Time
        6. 8.4.4.6 Pulse On Time
    5. 8.5 Programming
      1. 8.5.1 F/S Mode Protocol
      2. 8.5.2 DACx3401 I2C Update Sequence
      3. 8.5.3 Address Byte
      4. 8.5.4 Command Byte
      5. 8.5.5 I2C Read Sequence
    6. 8.6 Register Map
      1. 8.6.1  STATUS Register (address = D0h) (reset = 000Ch or 0014h)
        1. Table 18. STATUS Register Field Descriptions
      2. 8.6.2  GENERAL_CONFIG Register (address = D1h) (reset = 01F0h)
        1. Table 19. GENERAL_CONFIG Register Field Descriptions
      3. 8.6.3  MED_ALARM_CONFIG Register (address = D2h) (reset = 0000h)
        1. Table 20. MED_ALARM_CONFIG Register Field Descriptions
      4. 8.6.4  TRIGGER Register (address = D3h) (reset = 0008h)
        1. Table 21. TRIGGER Register Field Descriptions
      5. 8.6.5  DAC_DATA Register (address = 21h) (reset = 0000h)
        1. Table 22. DAC_DATA Register Field Descriptions
      6. 8.6.6  DAC_MARGIN_HIGH Register (address = 25h) (reset = 0000h)
        1. Table 23. DAC_MARGIN_HIGH Register Field Descriptions
      7. 8.6.7  DAC_MARGIN_LOW Register (address = 26h) (reset = 0000h)
        1. Table 24. DAC_MARGIN_LOW Register Field Descriptions
      8. 8.6.8  PMBUS_OPERATION Register (address = 01h) (reset = 0000h)
        1. Table 25. PMBUS_OPERATION Register Field Descriptions
      9. 8.6.9  PMBUS_STATUS_BYTE Register (address = 78h) (reset = 0000h)
        1. Table 26. PMBUS_STATUS_BYTE Register Field Descriptions
      10. 8.6.10 PMBUS_VERSION Register (address = 98h) (reset = 2200h)
        1. Table 27. PMBUS_VERSION Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Programmable LED Biasing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Power-Supply Margining
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Medical Alarm Generation
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 Programming

The DACx3401 devices have a 2-wire serial interface (SCL and SDA), and one address pin (A0), as shown in the Pin Configuration and Functions section. The I2C bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C-compatible devices connect to the I2C bus through the open drain I/O pins, SDA and SCL.

The I2C specification states that the device that controls communication is called a master, and the devices that are controlled by the master are called slaves. The master device generates the SCL signal. The master device also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus to indicate the start or stop of a data transfer. Device addressing is completed by the master. The master device on an I2C bus is typically a microcontroller or digital signal processor (DSP). The DACx3401 family operates as a slave device on the I2C bus. A slave device acknowledges master commands, and upon master control, receives or transmits data.

Typically, the DACx3401 family operates as a slave receiver. A master device writes to the DACx3401, a slave receiver. However, if a master device requires the DACx3401 internal register data, the DACx3401 operate as a slave transmitter. In this case, the master device reads from the DACx3401. According to I2C terminology, read and write refer to the master device.

The DACx3401 family is a slave and supports the following data transfer modes:

  • Standard mode (100 kbps)
  • Fast mode (400 kbps)
  • Fast+ mode (1.0 Mbps)

The data transfer protocol for standard and fast modes is exactly the same; therefore, both modes are referred to as F/S-mode in this document. The fast+ mode protocol is supported in terms of data transfer speed, but not output current. The low-level output current would be 3 mA; similar to the case of standard and fast modes. The DACx3401 family supports 7-bit addressing. The 10-bit addressing mode is not supported. The device supports the general call reset function. Sending the following sequence initiates a software reset within the device: start or repeated start, 0x00, 0x06, stop. The reset is asserted within the device on the rising edge of the ACK bit, following the second byte.

Other than specific timing signals, the I2C interface works with serial bytes. At the end of each byte, a ninth clock cycle generates and detects an acknowledge signal. Acknowledge is when the SDA line is pulled low during the high period of the ninth clock cycle. A not-acknowledge is when the SDA line is left high during the high period of the ninth clock cycle as shown in Figure 50.

DAC53401 DAC43401 Timing-2.gifFigure 50. Acknowledge and Not Acknowledge on the I2C Bus