SLASF08A December   2021  – May 2024 DAC43508 , DAC53508 , DAC63508

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configurations and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: SPI
    7. 5.7  Timing Requirements: Logic
    8. 5.8  Timing Diagrams
    9. 5.9  Typical Characteristics: Static Performance
    10. 5.10 Typical Characteristics: Dynamic Performance
    11. 5.11 Typical Characteristics: General
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 6.3.1.1 DAC Transfer Function
        2. 6.3.1.2 DAC Register Update and LDAC Functionality
        3. 6.3.1.3 CLR Functionality
        4. 6.3.1.4 Output Amplifier
      2. 6.3.2 Reference
      3. 6.3.3 Power-On Reset (POR)
      4. 6.3.4 Software Reset
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-Down Mode
    5. 6.5 Programming
      1. 6.5.1 Serial Peripheral Interface (SPI)
  8. 7 Register Map
    1. 7.1 DEVICE_CONFIG Register (address = 01h) [reset = 00FFh]
    2. 7.2 STATUS_TRIGGER Register (address = 02h) [reset = 0000h]
    3. 7.3 BRDCAST Register (address = 03h) [reset = 0000h]
    4. 7.4 DACn_DATA Register (address = 08h to 0Fh) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Programmable LED Biasing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Programmable Window Comparator
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RTE|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Revision History

Changes from Revision * (December 2023) to Revision A (May 2024)

  • Added DAC63508 and associated contentGo
  • Deleted INL from 1st Features bulletGo
  • Added exceptions for "current into any pin" in the Absolute Maximum Ratings Go
  • Updated footnotes in the Electrical characteristics Go
  • Added 12-bit resolution in Electrical Characteristics Go
  • Added INL data for 12-bit resolution in Electrical Characteristics Go
  • Updated DAC codes in the test conditions for DC output impedance in the Electrical Characteristics Go
  • Updated the reference input impedance value in the Electrical Characteristics Go
  • Moved plots and updated section titles to better organize all Typical Characteristics Go
  • Changed all plots to accommodate data for 12-bit resolution in all Typical Characteristics Go
  • Added the resolution information to the header test conditions for all Typical Characteristics Go
  • Updated plot test conditions for Figure 5-36, Glitch Impulse, Rising Edge, 4-LSB Step; Figure 5-37, Glitch Impulse, Falling Edge, 4-LSB Step; Figure 5-38, Full-Scale Settling Time, Rising Edge; Figure 5-39, Full-Scale Settling Time, Falling Edge in Typical Characteristics: Dynamic Performance Go
  • Changed "end of SPI frame" to "24th rising-edge of the clock" in DAC Register Update and LDAC Functionality Go
  • Changed from 12.5 kΩ to 24 kΩ in Reference Go
  • Changed 0x1010 to 1010b in Software Reset Go
  • Updated sentence to specify global power down current more accurately in Power-Down Mode Go
  • Updated BRDCAST_DATA and DACn_DATA bits from B11 till B0 in the Register Map Go
  • Changed Command Bits to Register Address in the Register Map table headerGo
  • Changed 1010 to 1010b in the STATUS_TRIGGER Register Go
  • Updated B11:B0 to accommodate 12-bit resolution in the DACn_DATA Register Go