SLASEW8A October   2020  – September 2023 DAC43701-Q1 , DAC53701-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Standard Mode
    7. 6.7  Timing Requirements: I2C Fast Mode
    8. 6.8  Timing Requirements: I2C Fast-Mode Plus
    9. 6.9  Timing Requirements: GPI
    10. 6.10 Timing Diagram
    11. 6.11 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
    12. 6.12 Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
    13. 6.13 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 7.3.1.1 Reference Selection and DAC Transfer Function
          1. 7.3.1.1.1 Power Supply as Reference
          2. 7.3.1.1.2 Internal Reference
      2. 7.3.2 General-Purpose Input (GPI)
      3. 7.3.3 DAC Update
        1. 7.3.3.1 DAC Update Busy
      4. 7.3.4 Nonvolatile Memory (EEPROM or NVM)
        1. 7.3.4.1 NVM Cyclic Redundancy Check
        2. 7.3.4.2 NVM_CRC_ALARM_USER Bit
        3. 7.3.4.3 NVM_CRC_ALARM_INTERNAL Bit
      5. 7.3.5 Programmable Slew Rate
      6. 7.3.6 Power-On Reset (POR)
      7. 7.3.7 Software Reset
      8. 7.3.8 Device Lock Feature
      9. 7.3.9 PMBus Compatibility
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down Mode
      2. 7.4.2 Continuous Waveform Generation (CWG) Mode
      3. 7.4.3 PMBus Compatibility Mode
    5. 7.5 Programming
      1. 7.5.1 F/S Mode Protocol
      2. 7.5.2 I2C Update Sequence
        1. 7.5.2.1 Address Byte
          1. 7.5.2.1.1 Target Address Configuration
        2. 7.5.2.2 Command Byte
      3. 7.5.3 I2C Read Sequence
    6. 7.6 Register Map
      1. 7.6.1  STATUS Register (address = D0h) [reset = 000Ch or 0014h]
      2. 7.6.2  GENERAL_CONFIG Register (address = D1h) [reset = 01F0h]
      3. 7.6.3  CONFIG2 Register (address = D2h) [reset = device-specific]
      4. 7.6.4  TRIGGER Register (address = D3h) [reset = 0008h]
      5. 7.6.5  DAC_DATA Register (address = 21h) [reset = 0000h]
      6. 7.6.6  DAC_MARGIN_HIGH Register (address = 25h) [reset = device-specific]
      7. 7.6.7  DAC_MARGIN_LOW Register (address = 26h) [reset =device-specific]
      8. 7.6.8  PMBUS_OPERATION Register (address = 01h) [reset = 0000h]
      9. 7.6.9  PMBUS_STATUS_BYTE Register (address = 78h) [reset = 0000h]
      10. 7.6.10 PMBUS_VERSION Register (address = 98h) [reset = 2200h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Power-Supply Margining
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 LED Thermal Foldback
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.2 Continuous Waveform Generation (CWG) Mode

The DACx3701-Q1 implement a continuous waveform generation feature. To set the device to this mode, set the START_FUNC_GEN (address D3h) to 1. In this mode, the DAC output pin (OUT) generates a continuous waveform based on the FUNC_CONFIG bits (address D1h). Table 7-6 shows the continuous waveforms that can be generated in this mode. The following equations show the frequency of the waveform depends on the resistive and capacitive load on the OUT pin, high and low codes, and slew rate settings.

Equation 3. f S Q U A R E = 1 2 × S L E W _ R A T E
Equation 4. f S A W T O O T H = 1 S L E W _ R A T E × C E I L I N G M A R G I N _ H I G H - M A R G I N _ L O W C O D E _ S T E P + 1
Equation 5. f T R I A N G L E = 1 2 × S L E W _ R A T E × C E I L I N G M A R G I N _ H I G H - M A R G I N _ L O W C O D E _ S T E P

where:

  • SLEW_RATE is the programmable DAC slew rate specified in Table 7-4.
  • MARGIN_HIGH and MARGIN_LOW are the programmable DAC codes.
  • CODE_STEP is the programmable DAC step code in Table 7-3.
  • CEILING is a function that returns the smallest integer value which is greater than or equal to the specified number.

The accuracy of the waveform frequencies depend on the accuracy of the internal oscillator. The DACx3701-Q1 support a calibration option to get the best oscillator frequency accuracy. The DAC-MARGIN-HIGH[11:4] register bits store the oscillator accuracy in the NVM in 2's compliment format. Any overwrite to these NVM bits clears this information permanently. The stored error resolution is 0.15% per LSB. Equation 6 calculates the percentage frequency error.

Equation 6. f E R R O R ( % ) = D A C _ M A R G I N _ H I G H [ 11 : 4 ] × 0.15
Table 7-6 FUNC_CONFIG bits
REGISTER ADDRESS AND NAME FUNC_CONFIG[1] FUNC_CONFIG[0] DESCRIPTION
D1h, GENERAL_CONFIG 0 0 Generates a triangle wave between MARGIN_HIGH (address 25h) code to MARGIN_LOW (address 26h) code with the slope defined by the SLEW_RATE and CODE_STEP (address D1h) bits.
0 1 Generates a sawtooth wave between MARGIN_HIGH (address 25h) code to MARGIN_LOW (address 26h) code, with the rising slope defined by the SLEW_RATE and CODE_STEP (address D1h) bits and immediate falling edge.
1 0 Generates a sawtooth wave between MARGIN_HIGH (address 25h) code to MARGIN_LOW (address 26h) code, with the falling slope defined by the SLEW_RATE and CODE_STEP (address D1h) bits and immediate rising edge.
1 1 Generates a square wave between MARGIN_HIGH (address 25h) code to MARGIN_LOW (address 26h) code with the pulse high and low period defined by the SLEW_RATE (address D1h) bits.