at TA = 25°C, VDD = 5.5 V,
external reference = 5.5 V, gain = 1 ×, 12-bit resolution, and DAC outputs unloaded
(unless otherwise noted)
![DAC53004W DAc63004W Voltage Output INL vs Digital Input Code GUID-20221107-SS0I-H8KG-CL3D-HMTQ846BT07K-low.svg](/ods/images/SLASF72/GUID-20221107-SS0I-H8KG-CL3D-HMTQ846BT07K-low.svg)
Internal reference, gain = 4 × |
Figure 6-4 Voltage Output INL vs Digital Input Code
Figure 6-6 Voltage Output INL vs Temperature![DAC53004W DAc63004W Voltage Output DNL vs Digital Input Code GUID-20221107-SS0I-BPRD-L4KT-XMQZKPH7H4JP-low.svg](/ods/images/SLASF72/GUID-20221107-SS0I-BPRD-L4KT-XMQZKPH7H4JP-low.svg)
Internal reference, gain = 4 × |
Figure 6-8 Voltage Output DNL vs Digital Input Code
Figure 6-10 Voltage Output DNL vs Temperature![DAC53004W DAc63004W Voltage Output TUE vs Digital Input Code GUID-20221107-SS0I-HXPW-MW54-V8QGSZXSLNN5-low.svg](/ods/images/SLASF72/GUID-20221107-SS0I-HXPW-MW54-V8QGSZXSLNN5-low.svg)
Internal reference, gain = 4 × |
Figure 6-12 Voltage Output TUE vs Digital Input Code
Figure 6-14 Voltage Output TUE vs Temperature
Figure 6-16 Voltage Output Offset Error vs Temperature
Figure 6-18 Voltage Output vs Load Current
Figure 6-20 Voltage Output Code-to-Code Glitch: Falling Edge![DAC53004W DAc63004W Voltage Output Setting Time: Falling Edge GUID-20211028-SS0I-ZWSW-N4VP-B2JWTJSZ2KG4-low.svg](/ods/images/SLASF72/GUID-20211028-SS0I-ZWSW-N4VP-B2JWTJSZ2KG4-low.svg)
Full
scale to zero scale swing |
Figure 6-22 Voltage Output Setting Time: Falling Edge
Figure 6-24 Voltage Output Power-Off Glitch![DAC53004W DAc63004W Voltage Output Noise Density GUID-20211028-SS0I-QZLC-9XXN-6RBHPLWPZWNR-low.svg](/ods/images/SLASF72/GUID-20211028-SS0I-QZLC-9XXN-6RBHPLWPZWNR-low.svg)
Internal reference, gain = 4 × |
Figure 6-26 Voltage Output Noise Density![DAC53004W DAc63004W Voltage Output Flicker Noise GUID-20211028-SS0I-GRVW-XMWF-KTWJZQTNFLTL-low.svg](/ods/images/SLASF72/GUID-20211028-SS0I-GRVW-XMWF-KTWJZQTNFLTL-low.svg)
Internal reference, gain = 4 ×, f = 0.1 Hz to 10
Hz |
Figure 6-28 Voltage Output Flicker Noise
Figure 6-30 Voltage Output AC PSRR vs Frequency
Figure 6-5 Voltage Output INL vs Digital Input Code
Figure 6-7 Voltage Output INL vs Supply Voltage
Figure 6-9 Voltage Output DNL vs Digital Input Code
Figure 6-11 Voltage Output DNL vs Supply Voltage
Figure 6-13 Voltage Output TUE vs Digital Input Code
Figure 6-15 Voltage Output TUE vs Supply Voltage
Figure 6-17 Voltage Output Gain Error vs Temperature
Figure 6-19 Voltage Output Code-to-Code Glitch - Rising Edge![DAC53004W DAc63004W Voltage Output Setting Time: Rising Edge GUID-20211028-SS0I-2GJL-SHNH-K1SFJJHZCH4W-low.svg](/ods/images/SLASF72/GUID-20211028-SS0I-2GJL-SHNH-K1SFJJHZCH4W-low.svg)
Zero
scale to full scale swing |
Figure 6-21 Voltage Output Setting Time: Rising Edge![DAC53004W DAc63004W Voltage Output Power-On Glitch GUID-20211028-SS0I-VGC7-JRDN-KM2NWKHZ61RB-low.svg](/ods/images/SLASF72/GUID-20211028-SS0I-VGC7-JRDN-KM2NWKHZ61RB-low.svg)
DAC
in Hi-Z power-down mode |
Figure 6-23 Voltage Output Power-On Glitch![DAC53004W DAc63004W Voltage Output Channel-to-Channel Crosstalk GUID-20211028-SS0I-BSQ4-Q7N9-HLZVQHRS3V49-low.svg](/ods/images/SLASF72/GUID-20211028-SS0I-BSQ4-Q7N9-HLZVQHRS3V49-low.svg)
Channel 2 is resident, all other channels are
interferers |
Figure 6-25 Voltage Output Channel-to-Channel Crosstalk
Figure 6-27 Voltage Output Noise Density
Figure 6-29 Voltage Output Flicker Noise