at
TA = 25°C, AVDD = 2.7 V, and DAC loaded with midscale code
(unless otherwise noted)
Figure 7-44 DAC7311 12-Bit Linearity Error and
Differential Linearity Error vs Code (–40°C)
Figure 7-46 DAC7311 12-Bit Linearity Error and
Differential Linearity Error vs Code (25°C)
Figure 7-48 DAC7311 12-Bit Linearity Error and
Differential Linearity Error vs Code (125°C)
Figure 7-50 DAC5311 8-Bit Linearity Error
and Differential Linearity Error vs Code (–40°C)
Figure 7-52 DAC5311 8-Bit Linearity Error
and Differential Linearity Error vs Code (25°C)
Figure 7-54 DAC5311 8-Bit Linearity Error
and Differential Linearity Error vs Code (125°C)
Figure 7-56 Source Current at Positive
Rail
Figure 7-58 Power-Supply Current vs Digital
Input Code 
Figure 7-60 Power-Supply Current vs Temperature 
Figure 7-62 Total Harmonic Distortion vs
Output Frequency 
Figure 7-64 Power Spectral Density
Figure 7-66 Clock Feedthrough 2.7-V,
20-MHz, Midscale
Figure 7-68 Glitch Energy, 2.7-V, 12-Bit,
1-LSB Step, Falling Edge
Figure 7-70 Glitch Energy, 2.7-V, 8-Bit, 1-LSB
Step, Falling Edge
Figure 7-72 Full-Scale Settling Time, 2.7-V
Falling Edge
Figure 7-74 Half-Scale Settling Time, 2.7-V
Falling Edge
Figure 7-76 Power-Off Glitch
Figure 7-45 DAC6311 10-Bit Linearity
Error and Differential Linearity Error vs Code (–40°C)
Figure 7-47 DAC6311 10-Bit Linearity
Error and Differential Linearity Error vs Code (25°C)
Figure 7-49 DAC6311 10-Bit Linearity Error
and Differential Linearity Error vs Code (125°C)
Figure 7-51 Zero-Code Error vs Temperature 
Figure 7-53 Offset Error vs Temperature 
Figure 7-55 Full-Scale Error vs Temperature 
Figure 7-57 Sink Current at Negative
Rail
Figure 7-59 Power-Supply Current vs Logic Input
Voltage 
Figure 7-61 Power-Down Current vs
Temperature 
Figure 7-63 Signal-to-Noise Ratio vs
Output Frequency 
Figure 7-65 Power-Supply Current
Histogram
Figure 7-67 Glitch Energy, 2.7-V, 12-Bit, 1-LSB
Step, Rising Edge
Figure 7-69 Glitch Energy, 2.7-V, 8-Bit, 1-LSB
Step, Rising Edge
Figure 7-71 Full-Scale Settling Time, 2.7-V
Rising Edge
Figure 7-73 Half-Scale Settling Time, 2.7-V
Rising Edge
Figure 7-75 Power-On Reset to 0-V Power-On
Glitch