SLASE30 October 2020 DAC43401-Q1 , DAC53401-Q1
PRODUCTION DATA
MSB | .... | LSB | ACK | MSB | ... | LSB | ACK | MSB | ... | LSB | ACK | MSB | ... | LSB | ACK |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Address (A) byte Section 8.5.2.1 |
Command byte Section 8.5.2.2 |
Data byte - MSDB | Data byte - LSDB | ||||||||||||
DB [31:24] | DB [23:16] | DB [15:8] | DB [7:0] |
After each byte is received, the DACx3401-Q1 family acknowledges the byte by pulling the SDA line low during the high period of a single clock pulse, as shown in Figure 8-6. These four bytes and acknowledge cycles make up the 36 clock cycles required for a single update to occur. A valid I2C address byte selects the DACx3401-Q1 devices.
The command byte sets the operating mode of the selected DACx3401-Q1 device. For a data update to occur when the operating mode is selected by this byte, the DACx3401-Q1 device must receive two data bytes: the most significant data byte (MSDB) and least significant data byte (LSDB). The DACx3401-Q1 device performs an update on the falling edge of the acknowledge signal that follows the LSDB.
When using fast mode (clock = 400 kHz), the maximum DAC update rate is limited to 10 kSPS. Using the fast mode plus (clock = 1 MHz), the maximum DAC update rate is limited to 25 kSPS. When a stop condition is received, the DACx3401-Q1 device releases the I2C bus and awaits a new start condition.