The DACx3401-Q1 implement a cyclic redundancy check (CRC) feature for the
device NVM to make sure that the data stored in the device NVM is uncorrupted. There
are two types of CRC alarm bits implemented in DACx3401-Q1:
- NVM_CRC_ALARM_USER
- NVM_CRC_ALARM_INTERNAL
The NVM_CRC_ALARM_USER bit indicates the status of user-programmable NVM bits,
and the NVM_CRC_ALARM_INTERNAL bit indicates the status of internal NVM bits The CRC
feature is implemented by storing a 10-Bit CRC (CRC-10-ATM) along with the NVM data
each time NVM program operation (write or reload) is performed and during the device
start up. The device reads the NVM data and validates the data with the stored CRC.
The CRC alarm bits (NVM_CRC_ALARM_USER and NVM_CRC_ALARM_INTERNAL address D0h)
report any errors after the data are read from the device NVM.