SLASES7A July   2019  – December 2019 DAC43401 , DAC53401

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Functional Block Diagram
      2.      Power-Supply Control With the DACx3401
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2CTM Standard mode
    7. 7.7  Timing Requirements: I2CTM Fast mode
    8. 7.8  Timing Requirements: I2CTM Fast+ mode
    9. 7.9  Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
    10. 7.10 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 Reference Selection and DAC Transfer Function
          1. 8.3.1.1.1 Power Supply as Reference
          2. 8.3.1.1.2 Internal Reference
      2. 8.3.2 DAC Update
        1. 8.3.2.1 DAC Update Busy
      3. 8.3.3 Nonvolatile Memory (EEPROM or NVM)
        1. 8.3.3.1 NVM Cyclic Redundancy Check
        2. 8.3.3.2 NVM_CRC_ALARM_USER Bit
        3. 8.3.3.3 NVM_CRC_ALARM_INTERNAL Bit
      4. 8.3.4 Programmable Slew Rate
      5. 8.3.5 Power-on-Reset (POR)
      6. 8.3.6 Software Reset
      7. 8.3.7 Device Lock Feature
      8. 8.3.8 PMBus Compatibility
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Down Mode
      2. 8.4.2 Continuous Waveform Generation (CWG) Mode
      3. 8.4.3 PMBus Compatibility Mode
      4. 8.4.4 Medical Alarm Generation Mode
        1. 8.4.4.1 Low-Priority Alarm
        2. 8.4.4.2 Medium-Priority Alarm
        3. 8.4.4.3 High-Priority Alarm
        4. 8.4.4.4 Interburst Time
        5. 8.4.4.5 Pulse Off Time
        6. 8.4.4.6 Pulse On Time
    5. 8.5 Programming
      1. 8.5.1 F/S Mode Protocol
      2. 8.5.2 DACx3401 I2C Update Sequence
      3. 8.5.3 Address Byte
      4. 8.5.4 Command Byte
      5. 8.5.5 I2C Read Sequence
    6. 8.6 Register Map
      1. 8.6.1  STATUS Register (address = D0h) (reset = 000Ch or 0014h)
        1. Table 18. STATUS Register Field Descriptions
      2. 8.6.2  GENERAL_CONFIG Register (address = D1h) (reset = 01F0h)
        1. Table 19. GENERAL_CONFIG Register Field Descriptions
      3. 8.6.3  MED_ALARM_CONFIG Register (address = D2h) (reset = 0000h)
        1. Table 20. MED_ALARM_CONFIG Register Field Descriptions
      4. 8.6.4  TRIGGER Register (address = D3h) (reset = 0008h)
        1. Table 21. TRIGGER Register Field Descriptions
      5. 8.6.5  DAC_DATA Register (address = 21h) (reset = 0000h)
        1. Table 22. DAC_DATA Register Field Descriptions
      6. 8.6.6  DAC_MARGIN_HIGH Register (address = 25h) (reset = 0000h)
        1. Table 23. DAC_MARGIN_HIGH Register Field Descriptions
      7. 8.6.7  DAC_MARGIN_LOW Register (address = 26h) (reset = 0000h)
        1. Table 24. DAC_MARGIN_LOW Register Field Descriptions
      8. 8.6.8  PMBUS_OPERATION Register (address = 01h) (reset = 0000h)
        1. Table 25. PMBUS_OPERATION Register Field Descriptions
      9. 8.6.9  PMBUS_STATUS_BYTE Register (address = 78h) (reset = 0000h)
        1. Table 26. PMBUS_STATUS_BYTE Register Field Descriptions
      10. 8.6.10 PMBUS_VERSION Register (address = 98h) (reset = 2200h)
        1. Table 27. PMBUS_VERSION Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Programmable LED Biasing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Power-Supply Margining
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Medical Alarm Generation
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤ VDD ≤ 5.5 V, DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) and capacitive load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution DAC53401 10 Bits
DAC43401 8
INL Relative accuracy(1) –1 1 LSB
DNL Differential nonlinearity(1) –1 1 LSB
Zero code error Code 0d into DAC 6 12 mV
Internal VREF, gain = 4x, VDD = 5.5 V 6 15
Zero code error temperature coefficient ±10 µV/°C
Offset error(1) –0.5 0.25 0.5 %FSR
Offset error temperature coefficient(1) ±0.0003 %FSR/°C
Gain error(1) –0.5 0.25 0.5 %FSR
Gain error temperature coefficient(1) ±0.0008 %FSR/°C
Full scale error 1.8 V ≤ VDD ≺ 2.7 V, code 1023d into DAC,
no headroom		 –1 0.5 1 %FSR
2.7 V ≤ VDD ≤ 5.5 V, code 1023d into DAC,
no headroom		 –0.5 0.25 0.5
Full scale error temperature coefficient ±0.0008 %FSR/°C
OUTPUT CHARACTERISTICS
Output voltage Reference tied to VDD 0 5.5 V
CL Capacitive load(2) RL = Infinite, phase margin = 30° 1 nF
RL = 5 kΩ, phase margin = 30° 2
Load regulation DAC at midscale, –10 mA ≤ IOUT ≤ 10 mA,
VDD = 5.5 V		 0.4 mV/mA
Short circuit current VDD = 1.8 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD 		10 mA
VDD = 2.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD 		25
VDD = 5.5 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD 		50
Output voltage headroom(1) To VDD (DAC output unloaded, internal reference = 1.21 V), VDD ≥ 1.21 ☓ gain + 0.2 V 0.2 V
To VDD 
(DAC output unloaded, reference tied to VDD)		 0.8 %FSR
To VDD (ILOAD = 10 mA at VDD = 5.5 V, ILOAD = 3 mA at VDD = 2.7 V, ILOAD = 1 mA at VDD = 1.8 V), DAC code = full scale 10
VOUT dc output impedance DAC output enabled and DAC code = midscale 0.25 Ω
DAC output enabled and DAC code = 4d 0.25
DAC output enabled and DAC code = 1016d 0.26
ZO VFB dc output impedance(3) DAC output enabled, DAC reference tied to VDD (gain = 1x) or internal reference (gain = 1.5x or 2x) 160 200 240 kΩ
DAC output enabled, internal VREF, gain = 3x or 4x 192 240 288
VOUT + VFB dc output leakage(2) At startup, measured when DAC output is disabled and held at VDD / 2 for VDD = 5.5 V 5 nA
Power supply rejection ratio (dc) Internal VREF, gain = 2x, DAC at midscale;
VDD = 5 V ±10%		 0.25 mV/V
DYNAMIC PERFORMANCE
tsett Output voltage settling time 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V 8 µs
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V, internal VREF, gain = 4x 12
Slew rate VDD = 5.5 V 1 V/µs
Power on glitch magnitude At startup (DAC output disabled), RL = 5 kΩ, CL = 200 pF 75 mV
At startup (DAC output disabled), RL = 100 kΩ 200
Output enable glitch magnitude DAC output disabled to enabled (DAC registers at zero scale, RL = 100 kΩ 250 mV
Vn Output noise voltage (peak to peak) 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V 34 µVPP
Internal VREF, gain = 4x, 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V 70
Output noise density Measured at 1 kHz, DAC at midscale, VDD = 5.5 V 0.2 µV/√Hz
Internal VREF, gain = 4x,, measured at 1 kHz, DAC at midscale, VDD = 5.5 V 0.7
Power supply rejection ratio (ac)(3) Internal VREF, gain = 4x, 200-mV 50 or 60 Hz sine wave superimposed on power supply voltage, DAC at midscale –71 dB
Code change glitch impulse ±1 LSB change around mid code (including feedthrough) 10 nV-s
Code change glitch impulse magnitude ±1 LSB change around mid code (including feedthrough) 15 mV
EEPROM
Endurance –40°C ≤ TA ≤ 85°C  20000 Cycles
1000
Data retention(2) TA = 25°C  50 Years
EEPROM programming write cycle time(2) 5 10 15 ms
DIGITAL INPUTS
Digital feedthrough DAC output static at midscale, fast+ mode, SCL toggling 20 nV-s
Pin capacitance Per pin 10 pF
POWER
Load capacitor - CAP pin(2) 0.5 15 µF
IDD Current flowing into VDD Normal mode, DACs at full scale, digital pins static 0.5 0.8 mA
DAC power-down, internal reference power down 80 µA
(1) Measured with DAC output unloaded. For external reference between end-point codes: 8d to 1016d for 10-bit resolution, 2d to 254d for 8-bit resolution. For internal reference VDD ≥ 1.21 x gain + 0.2 V, between end-point codes: 8d to 1016d for 10-bit resolution, 2d to 254d for 8-bit resolution.
(2) Specified by design and characterization, not production tested.
(3) Specified with 200-mV headroom with respect to reference value when internal reference is used.