SLASEW8A October   2020  – September 2023 DAC43701-Q1 , DAC53701-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Standard Mode
    7. 6.7  Timing Requirements: I2C Fast Mode
    8. 6.8  Timing Requirements: I2C Fast-Mode Plus
    9. 6.9  Timing Requirements: GPI
    10. 6.10 Timing Diagram
    11. 6.11 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
    12. 6.12 Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
    13. 6.13 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 7.3.1.1 Reference Selection and DAC Transfer Function
          1. 7.3.1.1.1 Power Supply as Reference
          2. 7.3.1.1.2 Internal Reference
      2. 7.3.2 General-Purpose Input (GPI)
      3. 7.3.3 DAC Update
        1. 7.3.3.1 DAC Update Busy
      4. 7.3.4 Nonvolatile Memory (EEPROM or NVM)
        1. 7.3.4.1 NVM Cyclic Redundancy Check
        2. 7.3.4.2 NVM_CRC_ALARM_USER Bit
        3. 7.3.4.3 NVM_CRC_ALARM_INTERNAL Bit
      5. 7.3.5 Programmable Slew Rate
      6. 7.3.6 Power-On Reset (POR)
      7. 7.3.7 Software Reset
      8. 7.3.8 Device Lock Feature
      9. 7.3.9 PMBus Compatibility
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down Mode
      2. 7.4.2 Continuous Waveform Generation (CWG) Mode
      3. 7.4.3 PMBus Compatibility Mode
    5. 7.5 Programming
      1. 7.5.1 F/S Mode Protocol
      2. 7.5.2 I2C Update Sequence
        1. 7.5.2.1 Address Byte
          1. 7.5.2.1.1 Target Address Configuration
        2. 7.5.2.2 Command Byte
      3. 7.5.3 I2C Read Sequence
    6. 7.6 Register Map
      1. 7.6.1  STATUS Register (address = D0h) [reset = 000Ch or 0014h]
      2. 7.6.2  GENERAL_CONFIG Register (address = D1h) [reset = 01F0h]
      3. 7.6.3  CONFIG2 Register (address = D2h) [reset = device-specific]
      4. 7.6.4  TRIGGER Register (address = D3h) [reset = 0008h]
      5. 7.6.5  DAC_DATA Register (address = 21h) [reset = 0000h]
      6. 7.6.6  DAC_MARGIN_HIGH Register (address = 25h) [reset = device-specific]
      7. 7.6.7  DAC_MARGIN_LOW Register (address = 26h) [reset =device-specific]
      8. 7.6.8  PMBUS_OPERATION Register (address = 01h) [reset = 0000h]
      9. 7.6.9  PMBUS_STATUS_BYTE Register (address = 78h) [reset = 0000h]
      10. 7.6.10 PMBUS_VERSION Register (address = 98h) [reset = 2200h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Power-Supply Margining
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 LED Thermal Foldback
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.4 TRIGGER Register (address = D3h) [reset = 0008h]

Figure 7-10 TRIGGER Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEVICE_UNLOCK_CODE X GPI_
EN		 DEVICE_
CONFIG_
RESET		 START_
FUNC_
GEN		 PMBUS_
MARGIN_
HIGH		 PMBUS_
MARGIN_
LOW		 NVM_
RELOAD		 NVM_
PROG		 SW_RESET
W-0h X-0 R/W-0 W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 W-8h
Table 7-19 TRIGGER Register Field Descriptions
Bit Field Type Reset Description
15:12 DEVICE_UNLOCK_CODE W 0h Write 0101 to unlock the device to bypass DEVICE_LOCK bit.
11 X X 0 Don't care
10 GPI_EN R/W 0 0: GPI disabled
1: GPI enabled
9 DEVICE_CONFIG_RESET W 0 0: Device configuration reset not initiated
1: Device configuration reset initiated. All registers loaded with factory reset values.
8 START_FUNC_GEN R/W 0 0: Continuous waveform generation mode disabled
1: Continuous waveform generation mode enabled, device generates continuous waveform based on FUNC_CONFIG (address D1h), MARGIN_LOW (address 26h), MARGIN_HIGH (address 25h), and SLEW_RATE and CODE_STEP (address D1h) bits.
7 PMBUS_MARGIN_HIGH R/W 0 0: PMBus margin high command not initiated
1: PMBus margin high command initiated, DAC output margins high to MARGIN_HIGH code (address 25h). This bit automatically resets to 0 after the DAC code reaches MARGIN_HIGH value.
6 PMBUS_MARGIN_LOW R/W 0 0: PMBus margin low command not initiated
1: PMBus margin low command initiated, DAC output margins low to MARGIN_LOW code (address 26h). This bit automatically resets to 0 after the DAC code reaches MARGIN_LOW value.
5 NVM_RELOAD R/W 0 0: NVM reload not initiated
1: NVM reload initiated, applicable DAC registers loaded with corresponding NVM. NVM_BUSY bit set to 1 which this operation is in progress.. This bit self-resets.
4 NVM_PROG R/W 0 0: NVM write not initiated
1: NVM write initiated, NVM corresponding to applicable DAC registers loaded with existing register settings. NVM_BUSY bit set to 1 which this operation is in progress. This bit self-resets.
3:0 SW_RESET W 8h 1000: Software reset not initiated
1010: Software reset initiated, DAC registers loaded with corresponding NVMs, all other registers loaded with default settings.