SLASEW8A October   2020  – September 2023 DAC43701-Q1 , DAC53701-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Standard Mode
    7. 6.7  Timing Requirements: I2C Fast Mode
    8. 6.8  Timing Requirements: I2C Fast-Mode Plus
    9. 6.9  Timing Requirements: GPI
    10. 6.10 Timing Diagram
    11. 6.11 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
    12. 6.12 Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
    13. 6.13 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 7.3.1.1 Reference Selection and DAC Transfer Function
          1. 7.3.1.1.1 Power Supply as Reference
          2. 7.3.1.1.2 Internal Reference
      2. 7.3.2 General-Purpose Input (GPI)
      3. 7.3.3 DAC Update
        1. 7.3.3.1 DAC Update Busy
      4. 7.3.4 Nonvolatile Memory (EEPROM or NVM)
        1. 7.3.4.1 NVM Cyclic Redundancy Check
        2. 7.3.4.2 NVM_CRC_ALARM_USER Bit
        3. 7.3.4.3 NVM_CRC_ALARM_INTERNAL Bit
      5. 7.3.5 Programmable Slew Rate
      6. 7.3.6 Power-On Reset (POR)
      7. 7.3.7 Software Reset
      8. 7.3.8 Device Lock Feature
      9. 7.3.9 PMBus Compatibility
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down Mode
      2. 7.4.2 Continuous Waveform Generation (CWG) Mode
      3. 7.4.3 PMBus Compatibility Mode
    5. 7.5 Programming
      1. 7.5.1 F/S Mode Protocol
      2. 7.5.2 I2C Update Sequence
        1. 7.5.2.1 Address Byte
          1. 7.5.2.1.1 Target Address Configuration
        2. 7.5.2.2 Command Byte
      3. 7.5.3 I2C Read Sequence
    6. 7.6 Register Map
      1. 7.6.1  STATUS Register (address = D0h) [reset = 000Ch or 0014h]
      2. 7.6.2  GENERAL_CONFIG Register (address = D1h) [reset = 01F0h]
      3. 7.6.3  CONFIG2 Register (address = D2h) [reset = device-specific]
      4. 7.6.4  TRIGGER Register (address = D3h) [reset = 0008h]
      5. 7.6.5  DAC_DATA Register (address = 21h) [reset = 0000h]
      6. 7.6.6  DAC_MARGIN_HIGH Register (address = 25h) [reset = device-specific]
      7. 7.6.7  DAC_MARGIN_LOW Register (address = 26h) [reset =device-specific]
      8. 7.6.8  PMBUS_OPERATION Register (address = 01h) [reset = 0000h]
      9. 7.6.9  PMBUS_STATUS_BYTE Register (address = 78h) [reset = 0000h]
      10. 7.6.10 PMBUS_VERSION Register (address = 98h) [reset = 2200h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Power-Supply Margining
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 LED Thermal Foldback
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.2 GENERAL_CONFIG Register (address = D1h) [reset = 01F0h]

Figure 7-8 GENERAL_CONFIG Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FUNC_
CONFIG		 DEVICE_
LOCK		 EN_
PMBUS		 CODE_STEP SLEW_RATE DAC_PDN REF_EN DAC_SPAN
R/ W-00 R/W-0 R/W-0 R/W-000 R/W-Fh R/W-10h R/W-0 R/W-00
Table 7-17 GENERAL_CONFIG Register Field Descriptions
Bit Field Type Reset Description
15:14 FUNC_CONFIG R/W 00 00: Generates a triangle wave between MARGIN_HIGH (address 25h) code to MARGIN_LOW (address 26h) code with slope defined by SLEW_RATE and CODE_STEP bits.
01: Generates Saw-Tooth wave between MARGIN_HIGH (address 25h) code to MARGIN_LOW (address 26h) code, with rising slope defined by SLEW_RATE and CODE_STEP bits and immediate falling edge.
10: Generates Saw-Tooth wave between MARGIN_HIGH (address 25h) code to MARGIN_LOW (address 26h) code, with falling slope defined by SLEW_RATE and CODE_STEP bits and immediate rising edge.
11: Generates a square wave between MARGIN_HIGH (address 25h) code to MARGIN_LOW (address 26h) code with pulse high and low period defined by SLEW_RATE bits.
13 DEVICE_LOCK R/W 0 0: Device not locked
1: Device locked, the device locks all the registers. This bit can be overwritten (unlock device) by writing 0101 to the DEVICE_UNLOCK_CODE bits (address D3h)
12 EN_PMBUS R/W 0 0: PMBus mode disabled
1: PMBus mode enabled
11:9 CODE_STEP R/W 000 Code step for programmable slew rate control.
000: Code step size = 1 LSB (default)
001: Code step size = 2 LSB
010: Code step size = 3 LSB
011: Code step size = 4 LSB
100: Code step size = 6 LSB
101: Code step size = 8 LSB
110: Code step size = 16 LSB
111: Code step size = 32 LSB
8:5 SLEW_RATE R/W Fh Slew rate for programmable slew rate control.
0000: 25.6 µs (per step)
0001: 32 µs (per step)
0010: 38.4 µs (per step)
0011: 44.8 µs (per step)
0100: 204.8 µs (per step)
0101:256 µs (per step)
0110: 307.2 µs (per step)
0111: 819.2 µs (per step)
1000: 1.6384 ms (per step)
1001: 2.4576 ms (per step)
1010: 3.2768 ms (per step)
1011: 4.9152 ms (per step)
1100: 12 µs (per step)
1101: 8 µs (per step)
1110: 4 µs (per step)
1111: No slew (default)
4:3 DAC_PDN R/W 10 00: Power up
01: Power down to 10 kΩ
10: Power down to high impedance (default)
11: Power down to 10 kΩ
2 REF_EN R/W 0 0: Internal reference disabled, VDD is DAC reference voltage, DAC output range from 0 V to VDD.
1: Internal reference enabled, DAC reference = 1.21 V, DAC output range is a function of DAC_SPAN.
1:0 DAC_SPAN R/W 00 Only applicable when internal reference is enabled.
00: Reference to VOUT gain = 1.5 ×
01: Reference to VOUT gain = 2 ×
10: Reference to VOUT gain = 3 ×
11: Reference to VOUT gain = 4 ×